Purpose The purpose of this paper is to examine the role of self-help groups (SHGs) in providing an environment for the empowerment of Indian rural women. The authors argue that the SHG empowerment strategy paves the way for the process of development of bottom-up empowerment of women. The authors argue that SHG is a systematic strategy and is not solely based on credit, but also incorporates many other dimensions necessarily required for developing an empowerment process. Design/methodology/approach A qualitative study was the choice of design due to the inherent inability of the structured surveys to understand women empowerment (Mayoux, 1998), as this study was basically interested in the women’s perception of their own empowerment. To explore their experience, a series of semi-structured interviews and focus group discussions were conducted. Findings The authors stand by the application of SHG empowerment strategy in India and go against the rhetoric statements that “top to bottom” approach does not lead to a significant bottom-up empowerment. Originality/value The survey was conducted by the authors in the vicinity of rural Jaipur, Rajasthan, India. Moreover, during the survey, it was found out that participation in SHG facilitates women to know the current state of disempowerment and provides them strength, capacity to come out from the status of drudgery, poverty and seclusion.

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bstractIn this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We propose a novel technique for path selection in module-level circuits and report efficient algorithms for delay test generation. MODET has been implemented and tested against a number of hierarchical circuits with impressive speedups in relation to gatelevel test generation. ~t~Q d~c t i Q nFor today's high speed integrated circuits, it is as important E o verify the timing behaviour of a circuit as it is to test the circuit for static faults such as the popular "stuckat" faults. The gate-delay and the path-delay fault models were introduced to test for the presence of timing faults in the circuit due to which the circuit may fail to function properly at the design clock speed. The path delay fault model will be used in this paper. A pair of test vectors must be applied to test for a path delay fault [5]. Many efficient algorithms have been reported in the literature for generation of delay tests [5, 6, 81. However, generating delay tests for a circuit of VLSI complexity can be quite time consuming due to several reasons (a) The number of paths, and hence the number of path delay faults, can be excessively large (b) The test generation for a single delay fault can be time consuming since most test generators used PODEM-like [2] backtracking algorithms and (c) When the circuit description is available at block-level (or macro-level), an overhead is encountered in the flattening of the netlist to gate-level. The situation can be improved in the following ways. Efficient path selection algorithms [3,4] can be used to reduce the size of the fault set. Improved delay test generators (such as the FAN-based algorithm described in [6] or the algorithm based on binary decision diagrams described in [l]) 'Nitin and P a d were B.Tech students in Electrical Engineering at JIT Delhi when this work was carried out. Nitin is working with Wipro Information Systems, Bangalore and Parul is with the Department of EECS, University of Michigan, Ann Arbor.can reduce the test generation time by reducing the number of backtracks or through the use of algebraic techniques). To alleviate the problem of flattening the hierarchical netlist, we propose in this paper a scheme to perform delay test generation at the module level itself. A module in this paper is a combinational logic block consisting of one or more logic gates; examples of modules are full adders, multiplexers, comparators, and so on. Our experimental results show that hierarchical delay testing can provide orders of magnitude speedup over gate-level test generation. To provide further speedups, we also report a path selection algorithm which works on hierarchical netlists. Recently, Pomeranz and Reddy 191 have reported a test generator for circuits composed of macro blocks when the internal gate-level impl...

Objective - "Change is the only constant" is a cliché but it is important to identify the factors which are changing to emerge as challenges before the military leadership of tomorrow. The societies are bound to be affected by the changes taking place in the environment. Generally, every society is affected by the four types of environmental factors. These are political, social, economic and technological. Since in India, democracy is deep rooted and the philosophy of the defence forces is same and has neither changed nor is likely to change, this factor is not under study here. So, the purpose is to study the impact of other environmental factors on selection of Defence Services Officers. Methodology/Technique - The study has been carried out by personally visiting all the Service Selection Centres of the Indian Armed Forces and presenting a questionnaire to large number of junior, middle and senior level serving and retired officers at various places. Only 449 officers responded which included 190 junior officers, 133 middle-level officers and 126 senior officers. The response was put through SPSS software system and analysed. Findings - The analysis clearly revealed that environmental changes in the society over a period of time do impact the qualities in the youth which have direct bearing on their selection for officers in the armed forces. Since the selection is based on finding the officers like qualities available or trainable in the youth, the impact of environmental factors is directly affecting the intake of the youth resulting in deficiency of officers' cadre in the armed forces. Novelty - The research contributes to develop scientific knowledge in environmental change effect on selection of defence officers. Type of Paper - Empirical Keywords: Qualities; Environment; Socio-Economic Changes; Armed Forces. JEL Classification: H56, J11.

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