Efficient delay test generation for modular circuits

Abstract

bstractIn this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We propose a novel technique for path selection in module-level circuits and report efficient algorithms for delay test generation. MODET has been implemented and tested against a number of hierarchical circuits with impressive speedups in relation to gatelevel test generation. ~t~Q d~c t i Q nFor today's high speed integrated circuits, it is as important E o verify the timing behaviour of a circuit as it is to test the circuit for static faults such as the popular "stuckat" faults. The gate-delay and the path-delay fault models were introduced to test for the presence of timing faults in the circuit due to which the circuit may fail to function properly at the design clock speed. The path delay fault model will be used in this paper. A pair of test vectors must be applied to test for a path delay fault [5]. Many efficient algorithms have been reported in the literature for generation of delay tests [5, 6, 81. However, generating delay tests for a circuit of VLSI complexity can be quite time consuming due to several reasons (a) The number of paths, and hence the number of path delay faults, can be excessively large (b) The test generation for a single delay fault can be time consuming since most test generators used PODEM-like [2] backtracking algorithms and (c) When the circuit description is available at block-level (or macro-level), an overhead is encountered in the flattening of the netlist to gate-level. The situation can be improved in the following ways. Efficient path selection algorithms [3,4] can be used to reduce the size of the fault set. Improved delay test generators (such as the FAN-based algorithm described in [6] or the algorithm based on binary decision diagrams described in [l]) 'Nitin and P a d were B.Tech students in Electrical Engineering at JIT Delhi when this work was carried out. Nitin is working with Wipro Information Systems, Bangalore and Parul is with the Department of EECS, University of Michigan, Ann Arbor.can reduce the test generation time by reducing the number of backtracks or through the use of algebraic techniques). To alleviate the problem of flattening the hierarchical netlist, we propose in this paper a scheme to perform delay test generation at the module level itself. A module in this paper is a combinational logic block consisting of one or more logic gates; examples of modules are full adders, multiplexers, comparators, and so on. Our experimental results show that hierarchical delay testing can provide orders of magnitude speedup over gate-level test generation. To provide further speedups, we also report a path selection algorithm which works on hierarchical netlists. Recently, Pomeranz and Reddy 191 have reported a test generator for circuits composed of macro blocks when the internal gate-level impl...