No abstract

Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents lowcost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wirebond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied.

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Defects due to process-design interaction have a systematic nature. Therefore they can have a profound impact on yield. The capability to detect (and correct) them is a requirement to continue tofollow Moore's law. Most of the systematic defects are detected during the pmcess development. These defects are detectable with test struchues or visual inspection tools. However some process marginalities will only show-up in the topology of 'real' designs. Moreover; these defects are often not detectable with stuck-at testing. We show two examples of process related defects which could only be detected with more advanced test methods such as transition fault testing and low voltage testing. To correct systematic problem, however; one should not only have the capability to detect &-fects but also to identifL them. Our examples show that other tests would have been far more sensitive in detecting systematic issues. Therefore the detection of systematic defects gives new requirements to test suites and can only be achieved with a shifi in the position of manufacturing test.