NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

Rosa, G. La; Guarin, F.; Rauch, S.E.; Acovic, A.; Lukaitis, J.; Crabbé, E.F.

doi:10.1109/relphy.1997.584274

Cited by 83 publications

(35 citation statements)

References 10 publications

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“…Although these equations remain as a fundamental building block for modeling and understanding NBTI in p-MOSFETs, deep submicron technologies may deviate somewhat from these predictions. 51 Deviations have been observed in the electric field dependence, the activation energies, and in the time evolution of interface and fixed trap creation. Depending on the gate oxide process and whether or not the oxide has received plasma-induced damage, the NBTI oxide electric field exponent m (E ox m ) lies in the range of 1.5рmр3.0.…”

Section: Fixed Chargementioning

confidence: 99%

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder

Babcock

2003

Journal of Applied Physics

932

396

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Section: Fixed Chargementioning

confidence: 99%

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder

Babcock

2003

Journal of Applied Physics

932

396

View full text Add to dashboard Cite

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“…5). This demonstrates that, although NBTI activates in HS devices under HCS as well, it is not as dominant as in the case of the I/O devices: In I/O devices, most of the channel remains populated with holes during stress, which cause NBTI-like degradation near the source, and only a small part of the channel near the drain is degraded by hot carriers [9].…”

Section: Methodsmentioning

confidence: 97%

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Mishra

Ioannou

Mitra³

et al. 2008

IEEE Electron Device Lett.

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Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V g = V d ), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V g = V d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V g = V d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias. Index Terms-Concurrent HCI-NBTI, hot carrier injection (HCI), negative bias temperature instability (NBTI), silicon-oninsulator (SOI).

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“…On the other hand, higher degradation is observed for the 0.15 lm device and the degradation measured in reverse mode is higher than that measured in the forward mode. Given the fact that NBTI is known to have a weak dependence on channel length [35,36], the NBTI contribution on the overall observed 0.15 lm device degradation should be approximately equal to the NBTI degradation of the 0.35 lm (slightly different due to different device heating). To check for possible recovery effects, after the stress was removed, the saturation current of the 0.15 lm device was monitored vs. relaxation time.…”

Section: Concurrent Nbti and Hci Degradationmentioning

confidence: 99%

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

Ioannou

2007

Solid-State Electronics

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NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies

Cited by 83 publications

References 10 publications

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

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