Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Abstract

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V g = V d ), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V g = V d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V g = V d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias. Index Terms-Concurrent HCI-NBTI, hot carrier injection (HCI), negative bias temperature instability (NBTI), silicon-oninsulator (SOI).

A Guideline for the Optimum Fin Width Considering Hot-Carrier and NBTI Degradation in MuGFETs

“…NBTI stress was applied with the gate electrode held at a constant negative bias of V GS = −1.5 V, and hot-carrier stress was applied at V GS = V DS = −1.5 V under temperature between 25 • C and 125 • C. For NBTI characterization, the on-thefly method using an Agilent B1500A precision semiconductor parameter analyzer was applied to avoid measurement errors. impact ionization due to the nonlocal effects and reduced series resistance [5] and the enhancement of floating-body effects [2] have been suggested. Since the substrate is floated during the experiment and the positive charges in NOx-BL enhance the floating-body effects [8], we believe that the enhanced impact ionization rate and/or the parasitic bipolar transistor effects play a dominant role in the increased device degradation with the increase of W F [9].…”

“…At present levels of gate oxide thickness and electric fields, negative-bias-temperature-instability (NBTI) and hotcarrier effects are reported to be serious reliability problem in nanometer-scale p-channel MuGFET (p-MuGFET) technologies. NBTI degradation is more significant for narrow FinFETs [2]- [4], and hot-carrier degradation at elevated temperature is more significant in devices with wider fins [5], [6]. Several studies on the influence of W F on the NBTI and hot-carrier degradations have been reported [2]- [6], but a study on the device design guidelines for determining the optimum W F and n F to maximize the device lifetime has not been investigated.…”

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

“…The mechanisms of TID effects and NBTI effects for SOI devices have been systematically studied [9]- [12]. However, the degradation mechanisms of SOI devices under the combined effect of TID and NBTI have not been well studied.…”

Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

“…Recently, silicon-on-insulator (SOI) technology has generated great interest because of its major advantages over its bulk counterpart including their latch-up immunity, high speed and density thanks to the complete dielectric isolation of transistors [8], [9]. Whereas, NBTI reliability research of SOI technology is not as extensive as bulk technology [10], [11]. Moreover, it is generally believed that NBTI is only related to the electric field perpendicular to the channel of MOSFETs, and does not depend on the transverse electric field along the channel direction [1].…”