2020
DOI: 10.1109/access.2020.2997463
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Investigation of Negative Bias Temperature Instability Effect in Partially Depleted SOI pMOSFET

Abstract: The negative bias temperature instability (NBTI) mechanisms for Core and input/output (I/O) devices from a 130 nm partially-depleted silicon on insulator (PDSOI) technology are investigated. The I/O device degrades more than the Core device under the same stress electric field due to the different gate oxide processes in these two types of devices. Both the oxide trap charge and interface trap lead to the transfer characteristics degradations of the device after NBTI. While the near interfacial traps result in… Show more

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Cited by 11 publications
(5 citation statements)
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“…The threshold voltage is changed from −0.32166V to −0.33182 V, and the shift is about 10.16 mV. It is caused by the interface trap at Si/SiO 2 and the trap charge generated in the gate oxide [ 2 ]. This paper verifies this phenomenon through TCAD simulation; the simulation results are shown in Figure 4 .…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…The threshold voltage is changed from −0.32166V to −0.33182 V, and the shift is about 10.16 mV. It is caused by the interface trap at Si/SiO 2 and the trap charge generated in the gate oxide [ 2 ]. This paper verifies this phenomenon through TCAD simulation; the simulation results are shown in Figure 4 .…”
Section: Resultsmentioning
confidence: 99%
“…With the shrinking size of the integrated circuit and the thinning gate oxide thickness of MOSFETs, negative bias temperature instability (NBTI) has become a major reliability issue in modern CMOS technology [ 1 ]. It mainly describes the performance degradation of the PMOSFET when operating at negative gate bias and high temperature, which is mainly manifested as the threshold voltage shift, transconductance drop, and saturate current decrease of the PMOSFET due to the interface trap at Si/SiO 2 and the trap charge generated in the gate oxide [ 2 ]. Researchers have proposed many models to interpret the degradation mechanism of NBTI, among which the reaction-diffusion (R-D) model has been widely applied [ 3 ].…”
Section: Introductionmentioning
confidence: 99%
“…In addition, the same devices without irradiation were selected and applied with the same NBTI stress for comparison. The NBTI lifetimes were extracted using the voltage step stress (VSS) technique [14] for both the irradiated and unirradiated devices, as illustrated in our previous works [15]. For the Core device, it was first stressed at Vgs=-2.1 V for 1000 s at room temperature, then at -2.4 V for another 1000 s. And so on until the stress voltage reached -3.9 V. For I/O device, it was stressed from Vgs=-4.5 V to Vgs=-7.5 V with a -0.5 V interval.…”
Section: Methodsmentioning
confidence: 99%
“…Nanostructured three dimensional channels allow effective electrostatic doping in the channel regions as well as excellent gate controllability [1,12,13]. In further miniaturizing field-effect transistors (FET), gate-bias stress stability is one of the crucial issues affecting FET performance; the electric field across the gate oxide (E OX ) increases up to 2-6 MV cm −1 as the thickness of the gate dielectric decreases [14][15][16][17]. On the other hand, as for oxide TFTs, the annealing treatment has been demonstrated as an effective way to improve the stability [18][19][20][21].…”
Section: Introductionmentioning
confidence: 99%