Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET

Abstract

The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was investigated by accelerated stress tests. The results show that NBTI leads to a threshold voltage negative shift, saturate drain current reduction and transconductance degradation of the PMOSFET. Next, the relationship between the threshold voltage shift and stress time, gate bias and temperature, and the channel length is investigated, and the NBTI lifetime prediction model is established. The results show that the NBTI lifetime of a 130 nm T-Gate PDSOI PMOSFET is approximately 18.7 years under the stress of VG = −1.2 V and T = 125 °C. Finally, the effect of the floating-body effect on NBTI of PDSOI PMOSFET is investigated. It is found that the NBTI degradation of T-Gate SOI devices is greater than that of the floating-body SOI devices, which indicates that the floating-body effect suppresses the NBTI degradation of SOI devices.

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

“…The changes obtained via applying negative voltage are denoted as NBTI, while changes obtained by applying positive voltage are denoted as PBTI (positive bias temperature instabilities). Moreover, from previous research and the literature [22,[24][25][26], it is known that larger changes occur at higher voltages, hence the results at −45 V are shown in this figure, too. An experiment involving stress at +45 V was not of interest.…”

“…The changes obtained via applying negative voltage are denoted as NBTI, while changes obtained by applying positive voltage are denoted as PBTI (positive bias temperature instabilities). Moreover, from previous research and the literature [22,[24][25][26], it is Regarding the fact that both NMOS and PMOS transistors were stressed, the results were obtained under both positive and negative gate voltages of 40 V, as presented in Figure 4. The changes obtained via applying negative voltage are denoted as NBTI, while changes obtained by applying positive voltage are denoted as PBTI (positive bias temperature instabilities).…”