Multiway FPGA partitioning by fully exploiting design hierarchy

Abstract

In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I/O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I/O-pin utilizations.

Intel nehalem processor core made FPGA synthesizable

“…However, compared to Atom, the Nehalem core requires roughly 4x more FPGA capacity. Due to this size increase, multiple-FPGA partitioning must be employed for the Nehalem core requiring time multiplexing of wires [2] between FPGAs and various partitioning tools [1] and techniques [5,12].…”

Multi‐FPGA Partitioning Method Based on Topological Levelization

“…In the past several years, many partitioning approaches and algorithms have been proposed to solve the FPGA partitioning problem [4][5][6][7][8][9][10]. One conventional partitioning approach for large netlists is to first apply clustering, topological ordering, and/or level construction schemes to reduce circuit complexity and then apply a set-covering method to reduce the number of required PEs.…”

Optimising physical wires usage in mesh-based multi-FPGA systems using partition swapping

“…The result of this partitioning approach is a set of segments of the synthesised design distributed over multiple devices [7], [11]. A number of studies have demonstrated the superiority of the partitioning at the behavioural level over RTL [6], [12], [13]. A common design representation for partitioning would be a graph-based model like Data Flow Graphs, Control and Data Flow Graphs [12] or Module Call Graphs [14].…”