This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.
Scalable architectures were proposed for Discrete Cosine Transform (DCT). Number of processing elements (PE) can be reduced significantly using partial column structure for computing the DCT transform. This feature is very desirable for multimedia applications usage in handheld devices. As per transform computation, data reordering is required between stages (columns) where intermediate computed values are saved in memory-like temporary locations called FIFO's. A scalable interconnect network for both global and local data reordering and its implementation is presented in this paper. Scalability is based on transform size and desired number of processing elements (PE). The structure gives choice flexibility of throughput vs. complexity (cost and area.) of the overall system.
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