In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I/O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I/O-pin utilizations.
We propose an integrated HDL-synthesis and placement method for row-based layouts. Our approach bridges the gap between HDL synthesis and placement by fully utilizing design hierarchy. It jkt synthesizes an HDL design specification into a hierarchy of subcircuits. It then groups subcircuits to form strongly connected macro cells, followed by performing a macrocell placement to determine the location of the macro cells on the layout plane. Finally, it maps the resulting macro-cell placement into a row-based placement and applies a simulated-annealing procedure to refine the row-based placement. Ezperiments on a number of large industry designs demonstrate that the proposed method achieves, on the average, 22% area T&L&On, 18% wire length reduction, and several times of speed up compared to that without the hierarchy information.
This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method c onsists of three steps: 1 functional-cluster formation, 2 slack computation, and 3 set-coveringbased p artitioning with functional replication. The proposed method p erforms multi-FPGA partitioning by taking into account path delays and design structural information. We intr oduce a functional replication technique which performs circuit replications at the functionalcluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions.
Louic emulation is a technique that uses dvnamically TepTogrammable systems for prototyping ad design verification.Usina an emulator. desianers can realize designs through a" software co&gun&on process and peTform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shodening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to Teplace portions of the design with macro cells. This paper presents a module generator foT logicemulation a.pplications, which is able to generate macro cells of arbitrarily complex functions described in Highlevel Descriptive Languages (HDLs). Furthermore, the module geneTutor can effectively generate a multiple-FPGA macro fOT large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are TepOTted. The Tesults demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Tkansfer-Level (RTL) description.In addition, the Tesults also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.
SUMMARYThis paper presents a cooperative design-view environment for interactive partitioning applications. This environment provides the user with a comprehensive viewing facility that describes the potentially complex relationships between various design objects. Using this environment, the user is able to evaluate and analyse design results visually throughout the entire partitioning process. We have developed a graphical user interface (GUI) environment for the ZnterPur system which supports mixed automatic and manual partitioning for multiple-field programmable gate array (FPGA) designs. The preliminary experiments have shown that the use of ZnterPur may lead to a new direction for the exploration of new partitioning approaches based on the circuit-structure analysis.
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