Preserving HDL synthesis hierarchy for cell placement

Tsay, Yu-Wen; Fang, Wen-Jong; Wu, Allen C.-H.; Lin, Youn-Long

doi:10.1145/267665.267709

Cited by 7 publications

(3 citation statements)

References 6 publications

(3 reference statements)

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“…These algorithms do not consider information embedded in the original design, since circuits are typically flattened before SA is run. Some previous work in ASIC placers suggest that high-level information and design hierarchy should be considered during both clustering [18] and placement [19]. Floorplanning (or hierarchical) approaches to placement, based on the design's hierarchy as specified in its RTL have been introduced [20] and [21].…”

Section: Applying High-level Informationmentioning

confidence: 99%

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Gharibian¹,

Shannon²,

Jamieson

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Field Programmable Gate Arrays (FPGAs) CAD flow run-time has increased due to the rapid growth in size of designs and FPGAs. Researchers are trying to find new ways to improve compilation time without degrading design performance. In this paper, we present a novel approach that identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach is an orthogonal optimization applicable in incremental design and physical optimization, and reduces placement run-time. Specifically, we present a new algorithm that analyzes designs post-placement to extract mediumgrained super-clusters that consist of two to seventeen clusters, which we call "gems". We modified VPR's simulated annealing placement algorithm to place our mixture of gems and clusters. Our new "Singularity Annealing" algorithm first crushes each cluster grouping into a "singularity" (treated as a single cluster). Then, the Singularity Annealer is run over this condensed circuit to obtain an initial placement, followed by an expansion of the singularities. Finally, we run a second low-temperature annealing phase on the entire expanded circuit. Our results show that our system reduces placement run-time on average by 17% while maintains the designs critical path delay, and increases designs channel width, and wirelength by 2% and 6.3%, respectively. We have also presented a test case to show the re-usability of gems in an incremental design example.

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Section: Applying High-level Informationmentioning

confidence: 99%

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Gharibian¹,

Shannon²,

Jamieson

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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“…The first one is to develop a method which can utilize design structural hierarchy to guide soft-macro placement. Several recent studies [14]- [20] have demonstrated that considering the circuit structural properties during the placement process can improve the placement result. In this study, we investigate how to preserve HDL design hierarchy to improve the quality of soft-macro placement, as shown in Fig.…”

Section: Problem Descriptionmentioning

confidence: 99%

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Lin

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area.

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“…Although we are interested in using system-level information for clustering algorithms and multiphased placement, we do not assume a fixed number of clusters per super-cluster (like the Ultra-Fast Placement algorithm [9]) or a fixed number of super-clusters (like the K-clustering algorithms [17] Design Level Information: FPGA placements based on SA use random initial placements and do not consider information embedded in the original design as circuits are typically flattened before SA is run. Some previous work in ASIC placers suggest that high-level information and design hierarchy should be considered during both clustering [18] and placement [19]. Previously, floorplanning (or hierarchical) approaches to placement, based on the design's hierarchy as specified in its RTL have been introduced [20], [21].…”

Section: Introductionmentioning

confidence: 99%

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

Gharibian

Shannon

Jamieson

2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information related to the original design hierarchy. Unfortunately, placement is an NP-hard problem and as the size and complexity of designs implemented on FPGAs increases, SA does not scale well to find good solutions in a timely fashion. As modern FPGAs can be used to implement Systems-and Networks-on-Chip, designers are required to spend an increasing amount of time waiting for place and route tools to complete that is not being matched by an increase in the power of computing work stations.In this paper, we investigate if system-level information can be reconstructed from a flattened netlist and evaluate how that information is realized in terms of its locality in the final placement. If there is a strong relationship between good quality placements and system-level information, then it may be possible to divide a large design into smaller components and improve the time needed to create a good quality placement. Our preliminary results suggest that the locality property of the information embedded in the system-level HDL structure (i.e. "module", "always", and "if" statements) is greatly affected by both the designer and the design itself. A reconstructive algorithm, called affinity propagation, is also considered as a possible method of generating a meaningful coarse grain picture of the design.

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Preserving HDL synthesis hierarchy for cell placement

Cited by 7 publications

References 6 publications

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

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