Performance-driven multi-FPGA partitioning using functional clustering and replication

Fang, Wen-Jong; Wu, Allen C.-H.

doi:10.1145/277044.277125

Cited by 14 publications

(2 citation statements)

References 10 publications

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“…Fang and Wu [19], [20] found that using the design hierarchy to guide partitioning would lead to higher logic block utilization and lower I/O pin utilization, which commonly formed the bottleneck when partitioning over multiple FPGAs, and resembles our avoidance of high-fanout paths. Some early work by Vahid, Frank, Le, and Hsu [21], [22] pointed to the advantages of functional partitioning, the kind we do in this paper, over structural partitioning, where partitioning occurs after the synthesis of a final, flattened netlist.…”

Section: Related Workmentioning

confidence: 99%

Maximizing speed and density of tiled FPGA overlays via partitioning

LaForest

Steffan

2013

2013 International Conference on Field-Programmable Technology (FPT)

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Common practice for large FPGA design projects is to divide sub-projects into separate synthesis partitions to allow incremental recompilation as each sub-project evolves. In contrast, smaller design projects avoid partitioning to give the CAD tool the freedom to perform as many global optimizations as possible, knowing that the optimizations normally improve performance and possibly area. In this paper, we show that for high-speed tiled designs composed of duplicated components and hence having multi-localities (multiple instances of equivalent logic), a designer can use partitioning to preserve multi-locality and improve performance. In particular, we focus on the lanes of SIMD soft processors and multicore meshes composed of them, as compiled by Quartus 12.1 targeting a Stratix IV EP4SE230F29C2 device. We demonstrate that, with negligible impact on compile time (less than ±10%): (i) we can use partitioning to provide high-level information to the CAD tool about preserving multi-localities in a design, without low-level micro-managing of the design description or CAD tool settings; (ii) by preserving multi-localities within SIMD soft processors, we can increase both frequency (by up to 31%) and compute density (by up to 15%); (iii) partitioning improves the density and speed (by up to 51 and 54%) of a mesh of soft processors, across many building block configurations and mesh geometries; (iv) the improvements from partitioning increase as the number of tiled computing elements (SIMD lanes or mesh nodes) increases. As an example of the benefits of partitioning, a mesh of 102 scalar soft processors improves its operating frequency from 284 up to 437 MHz, its peak performance from 28,968 up to 44,574 MIPS, while increasing its logic area by only 0.85%.

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Section: Related Workmentioning

confidence: 99%

Maximizing speed and density of tiled FPGA overlays via partitioning

LaForest

Steffan

2013

2013 International Conference on Field-Programmable Technology (FPT)

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“…This prototyping can drastically reduce the time required for software-based logic simulation of an ASIC, and it can expand test coverage by working as a hardware accelerator [1]. Various methods such as multi-FPGA partitioning [2] have been proposed to enhance this capability. When prototyping a system on FPGAs, interfaces and partial behaviors of external devices can be modeled precisely, and sets of stimuli generated from the models are fed to logic simulations running on the FPGAs.…”

Section: System Conceptmentioning

confidence: 99%

On-demand design service innovations

et al. 2004

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Offering design services for manufacturers of embedded devices has become a very important business, one in which the three leading customer requirements are time to market, integration of leading-edge technologies, and cost reduction; in short, ondemand design services. In this paper, we discuss on-demand design service innovations of several types. First, we discuss our unique field-programmable gate array (FPGA)-based system emulation tool. Although embedded systems comprise a wide range of technologies and components, some important technologies and components are common to most embedded systems. Security and communications are two of these, and we have developed offerings in these areas as well. For security, we developed scalable intellectual property macros to meet the requirements for many kinds of cryptographic circuits. These macros can satisfy specific requirements-performance, size of the silicon area, and power dissipation-for many kinds of embedded systems. For communications, we developed an autonomic network configuration tool which allows an end user to avoid the potential frustration of setting up a network connection and which also automatically performs network security tasks.

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