A domain specific language (DSL) enables designers to rapidly specify and implement systems for a particular domain, yielding designs that are easy to understand, reason about, re-use and maintain. However, there is usually a significant overhead in the required infrastructure to map such a DSL on to a programmable logic device. In this paper, we present a mapping of an existing DSL for the networking domain on to a platform FPGA by embedding the DSL into an existing language infrastructure. In particular, we will show that, using few basic concepts, we are able to achieve a successful mapping of the DSL on to a platform FPGA and create a re-usable structure that also makes it easy to extend the DSL. Finally we will present some results of mapping the DSL on to a platform FPGA and comment on the resulting overhead.
We present an FPGA-synthesizable version of the Intel R Atom TM processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium R -based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads.
In this paper, we present an intelligent physical layer for cognitive mesh networks. It is well recognized that wireless mesh networks suffer from the inherent property of per hop delay attributed to store and forward routing and channel contention. We show that an intelligent physical layer coupled with efficient traffic engineering and channel allocation mechanism will reduce latency. In this paper, we discuss the evolution of an OFDM receiver, with sufficient software control to aid reconfigurability, capable of receiving and decoding information on different set of subcarriers, and also capable of switching the incoming signals to a different part of the available spectrum on the fly. Equipped with this enhanced receiver we propose a mechanism for wireless wormhole routing, which employs frequency domain switching between subchannels where each subchannel is defined by a set of subcarriers. The OFDM receiver handles three primitives: transmit, receive and relay rather than just transmit or receive. Instead of a contention based, store and forward routing, a relay oriented physical layer has been proposed to reduce latency. The processing pipeline at an intermediate node no longer involves higher layer processing, and the hardware relays the incoming signal on-the-fly to a different part of the spectrum allowing for a full duplex transmission as the transmitter can relay signals while it is receiving on a different subchannel.
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