Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances

Alieu, J.; Skotnicki, T.; Josse, E.; Régolini, J. L.; Brémond, G.

doi:10.1109/vlsit.2000.852797

Cited by 16 publications

(11 citation statements)

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“…Moreover, Gaubert et al recently reported that the RMS value of the surface roughness could be related to the 1/ / noise f performance. 77 They observed a pronounced improvement of the 1/ / noise by f a factor of 100, achieved by an improved cleaning and gate oxidation process, which primarily was linked to a reduced microroughness of the interface. Thus, the mobility fluctuation noise mechanism seems more sensitive to the mobility than predicted by Eq.…”

Section: Crystalline Qualitymentioning

confidence: 95%

“…Several explanations have been suggested: velocity saturation, 11,73 more pronounced effects of pocket implantations for SiGe, 73-75 longer electrical channel length for SiGe due to reduced boron diffusion, 76 and strain relaxation effects for shorter channels. 74,77 Recently, drive current and transconductance enhancements down to 50-nm gate length have been demonstrated by using SiGe. 72 In the report, it was found that the transconductance increased with decreasing width of the SiGe channel, suggesting strain improvements from the field oxide or local loading effects altering the thickness and/or composition of the Si-cap/SiGe/Si-buffer stack in such a way that it improves the hole confinement in the SiGe channel.…”

Section: Device Structure and Characteristicsmentioning

confidence: 99%

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Low-Frequency Noise In Advanced Mos Devices

2007

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Section: Crystalline Qualitymentioning

confidence: 95%

Section: Device Structure and Characteristicsmentioning

confidence: 99%

Low-Frequency Noise In Advanced Mos Devices

2007

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“…An improvement by a factor of 1.8 in bulk PMOSFETs 94 and a factor of 1.45 in SOI PMOSFETs 95 has been found. An interesting approach was taken by J. Alieu et al 96 . They used one type of multiple SiGe well for both NMOSFETs and PMOSFETs to form strained PMOS and NMOS channels.…”

Section: Non-classical Cmosmentioning

confidence: 99%

Mosfet and Front-End Process Integration: Scaling Trends, Challenges, and Potential Solutions Through the End of the Roadmap

Zeitzoff¹,

Hutchby

Huff³

2003

Frontiers in Electronics

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The development of advanced MOSFETs for future IC technology generations is discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS). Starting from overall chip circuit requirements, MOSFET and front-end process integration technology requirements and scaling trends are discussed, as well as some of the key challenges and potential solutions. These include the use of high-k gate dielectrics, metal-gate electrodes, and perhaps the use of non-classical devices such as double-gate MOSFETs in the later stages of the ITRS. IntroductionBy following Moore's Law for over thirty-five years, the IC industry has rapidly and consistently scaled the design rules, increased the chip and wafer size, and improved the design of devices and circuits 1 ' 2 . As a result, chip speed and functional density have increased exponentially with time while chip power dissipation and cost per function have decreased exponentially with time 3 . In particular, the number of memory bits per chip has quadrupled every three to four years, while the speed of microprocessors has more than doubled every three years, based on the increase from about 2 MHz for the Intel® 8080 in the mid-1970's to well over 1 GHz for current leading-edge chips 4 . The design rules have been scaled from about 8 \im in 1972 to the 130 nm (0.13 urn) DRAM half pitch (which is defined as half the minimum metal or polysilicon pitch for dense features) of today's leading-edge technology. This is a reduction factor of about 0.87 per year, or (1/V2) ~ 0.7 in a time interval of between two and three years, where the (1/V2) factor is the traditional reduction in design rules between successive technology generations. However, because certain key material, process, and MOSFET limits are being approached, there are increasing problems in continuing to scale at this rate.In the International Technology Roadmap for Semiconductors (ITRS) 5 , the progression of the IC technology generations is projected over the next 15 years. The goal is to aid the IC industry and its supporting infrastructure (especially the material and equipment vendors and university and national laboratories researchers) in continuing to follow Moore's Law during that period. One key change in the most recent ITRS is a major acceleration in the scaling of the physical gate length (L g ) of the MOSFETs, where L g is the final, etched length at the bottom of the gate electrode. The L g projections for high-performance transistors from both the 1999 6 and 2001 7 ITRS are plotted in Figure 1. For any given year, the 2001 projection is reduced from the 1999 projection by an amount ranging from about 35% to 50%. Alternatively, the 2001 projections lead the 1999 projections by four to six years. This accelerated scaling is important because L g is

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“…The strained SiGe layer as the channel of the deep submicron metal-oxide-semiconductor field-effect transistors (MOSFETs) has been extensively studied recently for improving the performance of device. 1,2) In addition to the fact that the bulk carrier mobility of the SiGe layer is higher than that of the Si layer, the compressive strain of SiGe layer [3][4][5] and the quantum confinement effect induced by the offset of valence band between SiGe and Si 6) are both lead to the enhancement of hole mobility when the SiGe layer is deposited directly on the Si substrate. Consequently, the performance of p-channel MOSFET (pMOSFET) devices is predictably increased by using the SiGe channel.…”

Section: Introductionmentioning

confidence: 99%

Reliability of Strained SiGe Channel p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ultra-Thin (EOT=3.1 nm) N₂O-Annealed SiN Gate Dielectric

Chen

Chien

Chen

et al. 2005

Jpn. J. Appl. Phys.

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The p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) with 50-nm-thick Si0.85Ge0.15 channel and ultra-thin (EOT=3.1 nm) N2O-annealed SiN gate dielectric has been shown to have well-performing on/off and output characteristics. Several methodologies for the device reliability characterization, such as stress-induced-leakage-current (SILC), drain-avalanche-hot-carrier (DAHC) injection, channel hot-carrier (CHC) injection and negative-bias-temperature-instability (NBTI), have been used and the results were compared. In terms of the long-term degradation, the excellent quality of the N2O-annealed SiN gate dielectric can be firmly obtained because only negligible degradations have been found after stressing no matter which technique was employed. Even so, the experimental results have been compared and we found that the HC degradation is worse than the NBTI degradation and the channel-hot-carrier (CHC) stressing is the worst case for all kinds of reliability testing. Meanwhile, we have also verified that the interface state generation is the dominant mechanism responsible for the HC-induced degradation while the electron trapping dominates the device degradation for the NBTI stressing.

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Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances

Cited by 16 publications

References 1 publication

Low-Frequency Noise In Advanced Mos Devices

Low-Frequency Noise In Advanced Mos Devices

Mosfet and Front-End Process Integration: Scaling Trends, Challenges, and Potential Solutions Through the End of the Roadmap

Reliability of Strained SiGe Channel p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ultra-Thin (EOT=3.1 nm) N₂O-Annealed SiN Gate Dielectric

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Multiple SiGe well: a new channel architecture for improving both NMOS and PMOS performances

Cited by 16 publications

References 1 publication

Low-Frequency Noise In Advanced Mos Devices

Low-Frequency Noise In Advanced Mos Devices

Mosfet and Front-End Process Integration: Scaling Trends, Challenges, and Potential Solutions Through the End of the Roadmap

Reliability of Strained SiGe Channel p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ultra-Thin (EOT=3.1 nm) N2O-Annealed SiN Gate Dielectric

Contact Info

Product

Resources

About

Reliability of Strained SiGe Channel p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Ultra-Thin (EOT=3.1 nm) N₂O-Annealed SiN Gate Dielectric