Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

Pae, Sangwoo; Su, Tai-Chi; Denton, J.P.; Neudeck, G.W.

doi:10.1109/55.761012

Cited by 41 publications

(7 citation statements)

References 10 publications

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“…We choose a top layer of polycrystalline silicon (polysilicon) to provide good electrical conductivity for the device. Ideally, crystalline silicon (c-Si) would be used for both the top and bottom layers, but multiple layers of c-Si can only be obtained by nonstandard techniques such as wafer bonding [18], epitaxial overgrowth [19], or oxygen implantation [20]. Hydrogenated amorphous silicon (a-Si:H) can be used in horizontal slot waveguides with good loss values ~2-4 dB/cm [14][15][16][17], but this material is poorly suited for the proposed electrical-injection device due to very low electrical carrier mobility.…”

Section: Design and Fabricationmentioning

confidence: 99%

Slot waveguides with polycrystalline silicon for electrical injection

Preston¹,

Lipson²

2009

Opt. Express

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We demonstrate horizontal slot waveguides using high-index layers of polycrystalline and single crystalline silicon separated by a 10 nm layer of silicon dioxide. We measure waveguide propagation loss of 7 dB/cm and a ring resonator intrinsic quality factor of 83,000. The electric field of the optical mode is strongly enhanced in the low-index oxide layer, which can be used to induce a strong modal gain when an active material is embedded in the slot. Both high-index layers are made of electrically conductive silicon which can efficiently transport charge to the slot region. The incorporation of conductive silicon materials with high-Q slot waveguide cavities is a key step for realizing electrical tunneling devices such as electrically pumped silicon-based light sources.

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Section: Design and Fabricationmentioning

confidence: 99%

Slot waveguides with polycrystalline silicon for electrical injection

Preston¹,

Lipson²

2009

Opt. Express

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“…Here, a process called epitaxial lateral overgrowth (ELO) is used to grow the crystalline Si on top of the gate dielectric. 16) To target high bandwidth performance, the doping concentrations have been increased to 2 Â 10 17 /cm 3 for the Si slab and 1 Â 10 18 /cm 3 for the ELO-Si rib. Also, the distances between the metal contacts and the waveguide rib have been reduced by >40%.…”

Section: Ghz Modulatormentioning

confidence: 99%

High Speed Metal–Oxide–Semiconductor Capacitor-Based Silicon Optical Modulators

Liao¹,

Samara-Rubio²,

Liu³

et al. 2006

jjap

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Silicon photonics has recently attracted a great deal of attention because it offers an opportunity for low cost opto-electronic solutions for applications ranging from telecommunications down to chip-to-chip interconnect. One area of silicon photonics research that has seen an exceptional increase in activity and advancement is high speed silicon optical modulation. Within three years, modulation bandwidth has increased nearly three orders of magnitude from MHz range to 10 GHz range. This paper reviews two high speed silicon optical modulators with GHz bandwidth. It discusses in detail their design, performance, and limitations; and it outlines a path that can enable realization of further device improvements.

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“…1-6, seed windows are opened on an oxidized Si substrate. Epitaxial growth is initiated through the seed window in the presence of dichlorosilane which supplies the silicon [44,10,42,40,41]. The quality of devices fabricated on epitaxially grown layer can be as good as those in bulk silicon.…”

Section: Opportunities For Three-dimensional Integrationmentioning

confidence: 99%

“…Figure 1-6: Selective epitaxial growth of Si islands through seed windows for monolithic 3-D integration [44].…”

Section: O1mentioning

confidence: 99%

System-level performance evaluation of three-dimensional integrated circuits

Rahman¹,

Reif²

2000

IEEE Trans. VLSI Syst.

175

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As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

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Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

Cited by 41 publications

References 10 publications

Slot waveguides with polycrystalline silicon for electrical injection

Slot waveguides with polycrystalline silicon for electrical injection

High Speed Metal–Oxide–Semiconductor Capacitor-Based Silicon Optical Modulators

System-level performance evaluation of three-dimensional integrated circuits

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