Multiple chip planning for chip-interposer codesign

Ho, Yuan-Kai; Chang, Yao-Wen

doi:10.1145/2463209.2488767

Cited by 27 publications

(17 citation statements)

References 18 publications

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“…The paper of [5] uses a bipartite matching algorithm to solve the SAP in 2.5D ICs, but the algorithm of [5] does not consider the signal assignment for TSVs and cannot handle the multi-terminal signals. To make the comparison feasible, we modify our test cases by removing the multi-terminal signals and the signals connecting escaping points.…”

Section: Signal Assignment Resultsmentioning

confidence: 99%

“…Recently, the work of [5] deals with a chip-interposer codesign problem to minimize the wirelength in a 2.5D IC, which plans the locations of dies on an interposer as well as the locations of I/O buffers and macro blocks in each die by a simulated annealing (SA) method. Also, a bipartite-matching-based algorithm is adopted in [5] to assign signals to micro-bumps. The method of [5] can effectively reduce the wirelength among micro-blocks, I/O buffers, and microbumps.…”

Section: Introductionmentioning

confidence: 99%

“…Also, a bipartite-matching-based algorithm is adopted in [5] to assign signals to micro-bumps. The method of [5] can effectively reduce the wirelength among micro-blocks, I/O buffers, and microbumps. However, it does not consider multi-terminal signals and ignores the signals that have to be delivered to the escaping points.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Liu

Chang

Wang

2014

Proceedings of the 51st Annual Design Automation Conference

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Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D IC. Because long interconnects would degrade the performance of 2.5D ICs, the multi-die floorplanning problem and signal assignment problem for 2.5D ICs are critical. This paper presents an enumeration-based algorithm and a network-flow-based algorithm to solve the multi-die floorplanning and signal assignment problems in a 2.5D IC, respectively. Also, to speed up the floorplanning and signal assignment algorithms, several acceleration techniques are proposed. The experimental results reveal that this work can effectively reduce the total wirelength in a 2.5D IC and the acceleration techniques can significantly speed up the proposed algorithms.

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Section: Signal Assignment Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Liu

Chang

Wang

2014

Proceedings of the 51st Annual Design Automation Conference

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“…Since the number of dies is (so far) rather limited, it can be solved effectively or even optimally using tailored algorithms, even with pin assignment accounted for. However, most previous work applies probabilistic optimization [65], [66], which falls short of this prospect.…”

Section: Efficient and Optimal Die Placementmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…This paper completed the parasitic parameters extraction of the differential transmission path in the frequency of 100 MHz, the length of the routing trace, the parasitic resistance and the parasitic capacitance, the parasitic inductance, mutual capacitance and mutual inductance are shown in Tab. 2 Tab.2 Parasitic parameters extraction Scattering parameters analysis. This papers also conducted extraction of scattering parameter, and the sweep frequency is set to 100MHz to 20GHz, and the insertion loss and the return loss were obtained.…”

Section: Modelingmentioning

confidence: 99%

Study on Electrical Performance of FC and WB in IC Ceramic Package

Wang¹,

Zhao²,

Yao³

et al. 2016

Proceedings of the 2016 3rd International Conference on Materials Engineering, Manufacturing Technology and Control

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Abstract. As the signal frequency of integrated circuit keeps increasing, parasitic effects caused by the interconnect transmission structure used in IC ceramic package is becoming important factor which will influence the transmission performance of the signal path. In this paper, parasitic parameters (Resistance, Capacitance and Inductance) and scattering parameters of the differential pair are analyzed through three-dimensional electromagnetic software simulation based on the characterization of ceramic package structure. Then from the point of scattering parameters, the frequency domain whether wire bonding or flip chip is suitable is also analyzed. The result showed that the return loss of wire bonding interconnection would be great when the signal frequency is above 5GHz, and flip chip would improve the transmission performance of high-frequency signal remarkably when compared with wire bonding in the condition of same routing, and so flip chip is preferably in high-speed IC package.

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Multiple chip planning for chip-interposer codesign

Cited by 27 publications

References 18 publications

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Study on Electrical Performance of FC and WB in IC Ceramic Package

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