Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

Abstract

Interposer-based 3D ICs (or known as 2.5D ICs) have been seen as an alternative approach to true 3D stacked ICs, which mount multiple dies on a silicon interposer and route signals between dies by the interconnects in the interposer. However, the floorplan of dies on the interposer and the signal assignment for macro-bumps and TSVs will largely impact the wirelength of the interconnects in a 2.5D IC. Because long interconnects would degrade the performance of 2.5D ICs, the multi-die floorplanning problem and signal assignment problem for 2.5D ICs are critical. This paper presents an enumeration-based algorithm and a network-flow-based algorithm to solve the multi-die floorplanning and signal assignment problems in a 2.5D IC, respectively. Also, to speed up the floorplanning and signal assignment algorithms, several acceleration techniques are proposed. The experimental results reveal that this work can effectively reduce the total wirelength in a 2.5D IC and the acceleration techniques can significantly speed up the proposed algorithms.

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…The authors of Ref. [67] apply an enumerative search to identify optimal die positions before using a pin assignment routine. This method, however, does not scale beyond six dies.…”

“…For example, the authors of Ref. [67] use a network-flow algorithm to establish the connections between I/O buffers and micro-bumps with the goal of minimizing the external wirelength. The approach in Ref.…”

A Length Matching Routing Algorithm for Set-Pair Routing Problem

“…In the routing design such as silicon interposer [1], [2], printed circuit board and etc., the combination of a pin pair to be connected by wire is often flexible when a wire is required to connect passive elements, I/O pins of reconfigurable chip or etc. In such cases, the number of signals to be propagated and the locations of pins are given as a problem instance specification.…”

“…In a basic set-pair routing problem, whether the connection requirements can be achieved is easily checked by network flow algorithms. Also, a set of wires that achieves the minimum total wire length can be obtained by obtaining a minimum cost maximum flow which can be obtained by a polynomial time [2], [9]. However, it is not easy to achieve the length matching of wires even if there exists a flexibility on pin pairs.…”

“…In such cases, whether the connection requirements can be achieved is easily checked by network flow algorithms. Moreover, the total wire length of connections can be minimized by finding a minimum cost maximum flow as used in [2]. However, the length difference of wires is often large even when the total wire length is minimized.…”