2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) 2018
DOI: 10.1109/aspdac.2018.8297375
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Optimal die placement for interposer-based 3D ICs

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Cited by 15 publications
(2 citation statements)
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“…The floorplan affects the overall area, the routing wirelength, the thermal effects, and the reliability of the design. Prior arts [20], [21] only consider the area and wirelength of the floorplan, while ignoring the performance metrics, such as the data movement frequency and communication latency between different chiplets. If the optimization of the floorplan can take the performance metrics into consideration, the final performance of the chiplet system can be improved.…”
Section: Floorplan Of Chipletsmentioning
confidence: 99%
“…The floorplan affects the overall area, the routing wirelength, the thermal effects, and the reliability of the design. Prior arts [20], [21] only consider the area and wirelength of the floorplan, while ignoring the performance metrics, such as the data movement frequency and communication latency between different chiplets. If the optimization of the floorplan can take the performance metrics into consideration, the final performance of the chiplet system can be improved.…”
Section: Floorplan Of Chipletsmentioning
confidence: 99%
“…In the physical layer, Funke et al [14] have proposed various algorithms that exhaustively search for optimal placement and routing solutions for up to six chiplets. The recent work of Osmonolovskyi et al [24] handles up to 11-chiplet design complexity using pruning methods. Minz et al [22] and Fang et al [13] focus on routing of inter-chiplet links on an interposer.…”
Section: Related Workmentioning
confidence: 99%