2018
DOI: 10.1109/jstqe.2018.2832654
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Monolithically Integrated CMOS-Compatible III–V on Silicon Lasers

Abstract: CMOS-compatible III-V lasers integrated on silicon are a crucial step to reduce power consumption and cost for nextgeneration optical transceivers. Here, we demonstrate a concept to co-integrate III-V lasers into a CMOS Silicon Photonics platform, in which lasers, photonics, and electronic circuitry share the same back end of line. Based on a bonded III-V epitaxial layer stack, ultra-thin laser devices, optically pumped lasing and coupling to silicon are demonstrated. Furthermore, we present all building block… Show more

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Cited by 29 publications
(20 citation statements)
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“…Most importantly, cw and pulsed laser operation with ultra-low lasing thresholds of 0.8-1.1 kW cm −2 are demonstrated. These values are significantly lower than any value reported for group-IV lasers, and are even comparable to those for epitaxially grown III-V InP laser 41 , or InGaAs lasers bonded on Si wafers 42 , albeit the latter operate at room temperature. This achievement relies on using dilute GeSn alloys with just 5.4 at.…”
Section: Resultsmentioning
confidence: 46%
“…Most importantly, cw and pulsed laser operation with ultra-low lasing thresholds of 0.8-1.1 kW cm −2 are demonstrated. These values are significantly lower than any value reported for group-IV lasers, and are even comparable to those for epitaxially grown III-V InP laser 41 , or InGaAs lasers bonded on Si wafers 42 , albeit the latter operate at room temperature. This achievement relies on using dilute GeSn alloys with just 5.4 at.…”
Section: Resultsmentioning
confidence: 46%
“…To this end, a potential on-board layout of the 40 Gb/s C2C interconnect will probably eliminate the need for SOAs in the transmission lines, turning C2C energy consumption into a parameter that depends solely on the power requirements of the RM and its respective electronic driver, the PD-TIA and the external LD that feeds the RM with the CW optical beam. Considering the employment of state-ofthe-art RM drivers [138] and assuming an LD with 6.1 dBm output power and a 10% wall-plug efficiency, the energy efficiency of the proposed 40 Gb/s C2C photonic link was estimated at 5.95 pJ/bit that increases to 6.25 pJ/bit when incorporating also state-of-the-art SerDes [139] , assuming a LD-to-RM coupling loss of 3dB [140], a RM insertion loss of 1.5 dB, 0.5dB for every Silicon-to-polymer and polymer-to-Silicon waveguide coupling [131] and an AWGR channel insertion loss of 6dB [135]. These energy efficiency values suggest a 63.3% and 61.4% improvement, respectively, compared to the 16.2 pJ/bit link energy efficiency of Intel QPI [134].…”
Section: A 40 Gb/s C2c Experimental Setup and Resultsmentioning
confidence: 99%
“…For the co-integration of the light source and the gain material, we explored a novel approach that goes beyond today's established III-V on silicon photonics concepts [23]. We embed the III-V layer in between the front-and back-end of the line of the silicon stack while the laser feedback structures are integrated into the silicon waveguide layer [24]. This will enable a monolithic co-integration of passive and active photonic functions together with electrical (Bi)CMOS circuits.…”
Section: Light Sourcesmentioning
confidence: 99%