Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

Samal, Sandeep Kumar; Nayak, Deepak Kumar; Ichihashi, Motoi; Banna, Srinivasa; Lim, Sung Kyu

doi:10.1109/s3s.2016.7804405

Cited by 54 publications

(21 citation statements)

References 2 publications

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“…Consequently, the cutsize is proportional to the number of Monolithic Interlayer Vias (MIVs). In monolithic 3D, MIVs are as small as regular vias, 50 nm [4], thus their number does not affect PPA results.…”

Section: A 3dic Tier Partitioningmentioning

confidence: 99%

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Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Sketopoulos

Sotiriou

Pavlidis

2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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In this work, we investigate the effect of metal stack and tier 3D IC partitioning methodologies on the Quality of Results (QoR) of monolithic 3D circuits compared to their 2D counterparts. Two interconnect options are considered. For the interconnect option, termed Single, a single metal stack is used where cell pins lie on two lower metal layers. A Face to Face (F2F) interconnect option is also considered where cell pins lie on symmetrical lower and upper metal layers in two different tiers. In addition, two 3D circuit partitioning methodologies are investigated including the Greedy Bin-Based Fidducia-Mattheyses (GBBFM) and a Displacement-based 3D Legaliser (3DLG). For both the 2D and 3D circuits, a multi-pass timing-driven In-Place Optimisation (IPO) is performed with an industrial P&R tool to extract the best QoR. For the 3D circuits, the IPO is applied after tier partitioning. The 45 nm nanoCAS library, a 3D library based on NANGATE 45 nm, is utilized and three typical benchmark circuits are analysed. The performance of 3D circuits is improved between 1% to 3%, total wirelength is significantly reduced, via usage is increased, yet the estimated power and cell area do not necessarily decrease. Single metal stack overall demonstrates better QoR than F2F integration.

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Section: A 3dic Tier Partitioningmentioning

confidence: 99%

“…Prior art (e.g. [1], [2], [3], [4], [5]) utilizes conventional 2D EDA tools, within a 3D flow, for implementing 3D ICs. Based on these tools, these works place and route (P&R) the circuits in several tiers (typically two) and aim to optimise Power, Performance, Area (PPA), connectivity between tiers, and thermal issues.…”

Section: Introductionmentioning

confidence: 99%

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Sketopoulos

Sotiriou

Pavlidis

2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…It has been argued that 3D-stacking was not practical for fine-grained 3D partitioning [7] due to the size of Through Silicon Vias (TSVs), and that a monolithic 3D-integration was the way to go. However, monolithic 3D still needs to solve some key showstoppers such as thermal budgets required for sequential Front End Of Line processing (i.e.…”

Section: A Problem Statement and Existing Solutionsmentioning

confidence: 99%

3D-Stacked Integrated Circuits: How Fine Should System Partitioning Be?

Delhaye

Milojevic

Goossens

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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3D stacked ICs package multiple, independently manufactured dies to reduce total system wire-length, improve timing, and reduce area and power. When designing stacked 3D-ICs, arises the question of the grain at which one should consider system partitioning to optimize the gains. This work uses known MAX-CUT graph partitioning algorithms to split designs from 42k up to 800k gates, with gates clustered from 8 and up to 32768 partitions. It has been found that with 2048 clusters, i.e. 20 to 400 gates per cluster depending on the design, a partitioning of the system allows on average to cut 35% of the nets that account for 73% of the total wire-length in 3D.

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“…For placement, routing, and design closure of monolithic 3D ICs, the reuse of commercial 2D physical design tools has been demonstrated to lower the barrier for industry-wide acceptance [40], [47], [48], [49]. Nevertheless, due to its sequential processing nature, such 3D ICs cannot apply "plug-and-play" in- * 2 For example, the micro-bump bonding in TSV-based 3D ICs may be underfilled with BCB polymer layers.…”

Section: Monolithic 3d Icsmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET technology

Cited by 54 publications

References 2 publications

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

3D-Stacked Integrated Circuits: How Fine Should System Partitioning Be?

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

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