3D-Stacked Integrated Circuits: How Fine Should System Partitioning Be?

Abstract

3D stacked ICs package multiple, independently manufactured dies to reduce total system wire-length, improve timing, and reduce area and power. When designing stacked 3D-ICs, arises the question of the grain at which one should consider system partitioning to optimize the gains. This work uses known MAX-CUT graph partitioning algorithms to split designs from 42k up to 800k gates, with gates clustered from 8 and up to 32768 partitions. It has been found that with 2048 clusters, i.e. 20 to 400 gates per cluster depending on the design, a partitioning of the system allows on average to cut 35% of the nets that account for 73% of the total wire-length in 3D.

Impact of Gate-Level Clustering on Automated System Partitioning of 3d-Ics

“…For both geometrical clustering methods, a grain of 1000 clusters has been selected, as it displays a profitable ratio of intra-cluster wires versus inter-cluster wire-length [23]. As for the progressive-wire-length method, the target maximum WL to be absorbed inside clusters has been set so that the resulting Min-cut partitioning could still be balanced, which came to be 100 times the average-gate-width of the design.…”