Modeling of Power Supply Noise in Large Chips Using the Circuit-Based Finite-Difference Time-Domain Method

Choi, Jinseong; Swaminathan, Madhavan; Do, Nhon; Master, R.N.

doi:10.1109/temc.2005.851719

Cited by 36 publications

(17 citation statements)

References 23 publications

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“…Simple as it is, the non-linearity of the I/O buffer is ignored and the negative feedback effect of the driver circuitry cannot be captured [5], [19]. The negative feedback effect is important, for example when we consider the relationship between SSN and the number of switching I/O buffers: It results in a sub-linear function that will saturate as shown in Fig.…”

Section: Chip Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity.We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to select proper ones for board-package-chip co-simulation and co-design of SSN. We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.

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Section: Chip Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Hence, the burden is on the packaging community to ensure that the package power distribution models interface well with the on-chip power distribution tools. Some aspects of chip-package co-simulation is available in [53]. In [44], the models in [53] have been extended for analytically extracting the parasitics of the on-chip power distribution through conformal mapping and simulation of the noise voltage using FDTD method.…”

Section: Modeling Of Power Distribution Networkmentioning

confidence: 99%

“…An important parameter for wafer level packaging to be attractive is the loop inductance between the voltage and ground rails, which is dictated by the compliant (or rigid) interconnect length and pitch. Preliminary simulations [53] based on ITRS 2005 (and beyond) indicate an inductance of 50 pH per interconnection for 5% noise tolerance on a 100-200-m pitch. In [53], the power supply noise was simulated for various interconnect technologies with inductances in the range 20 pH-2 nH to determine the optimum inductance required for the ITRS'05 node.…”

Section: System On a Package Technologiesmentioning

confidence: 99%

“…Preliminary simulations [53] based on ITRS 2005 (and beyond) indicate an inductance of 50 pH per interconnection for 5% noise tolerance on a 100-200-m pitch. In [53], the power supply noise was simulated for various interconnect technologies with inductances in the range 20 pH-2 nH to determine the optimum inductance required for the ITRS'05 node. The simulation assumed that the number of layers in Silicon was 4, the size of the chip was 20.1 mm 27 mm, the number of power/ground interconnects was 2464, the number of CMOS inverters switched was 77616, 40% of the total power was switched and the on-chip decoupling capacitance was 400 nF.…”

Section: System On a Package Technologiesmentioning

confidence: 99%

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Power distribution networks for system-on-package: status and challenges

Swaminathan

Kim

Novak

et al. 2004

IEEE Trans. Adv. Packag.

Self Cite

229

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Abstract-The power consumption of microprocessors isincreasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

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“…New architectures are being proposed for supporting terabit data rate speeds between processors (such as by Hofstee in this issue [10]. In addition, for memory channel, interconnection speeds greater than 3.2 Gb/s are being developed [11]. For the first time, the International Technology Roadmap on Semiconductors (ITRS) [12] is proposing the convergence of on-chip and off-chip clock speeds, with a goal of 5 GHz clock speed in the near future.…”

Section: Digital Sop: Design and Fabricationmentioning

confidence: 99%

The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade

Tummala

Swaminathan

Tentzeris

et al. 2004

IEEE Trans. Adv. Packag.

Self Cite

135

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Abstract-From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, IC's are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

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Modeling of Power Supply Noise in Large Chips Using the Circuit-Based Finite-Difference Time-Domain Method

Cited by 36 publications

References 23 publications

Modeling and design for beyond-the-die power integrity

Modeling and design for beyond-the-die power integrity

Power distribution networks for system-on-package: status and challenges

The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade

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