Modeling and design for beyond-the-die power integrity

Shi, Yiyu; He, Lei

doi:10.1109/iccad.2010.5653721

Cited by 6 publications

(2 citation statements)

References 28 publications

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“…The package and MB consist of discrete on-package/onboard intentional decap and also contribute parasitic inductance, which may change the system resonant behavior [2]- [4], [8]- [10]. Because of the larger electric-size and irregular geometry, the on-package model parasitics vary significantly with frequency and cannot be simply treated as quasi-static.…”

Section: Package/mb Modelingmentioning

confidence: 99%

Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

Zhuo

Wilke

Chakraborty

et al. 2015

IEEE Trans. VLSI Syst.

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Power integrity has become increasingly important for the designs in 32 nm or below. This paper discusses a siliconvalidated methodology for power delivery (PD) modeling and simulation. Many prior works have focused on PD analysis and optimization. However, none of them provided a comprehensive modeling methodology with postsilicon data to validate the use of the models. In this paper, we present PD system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32-nm industrial double date-rate I/O design. Our models are able to capture the unique impacts of on-die inductance, state-dependent coupling capacitance, and diepackage interaction. Those impacts are prominent for the designs in 32 nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for PD analysis.

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Section: Package/mb Modelingmentioning

confidence: 99%

Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

Zhuo

Wilke

Chakraborty

et al. 2015

IEEE Trans. VLSI Syst.

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“…On the other hand, an over-designed grid may render additional area and hence higher overall mask cost. In view of this, various methods [4][5][6][7][8][9][10][11][12][13][14][15][16][17] have been proposed for power grid analysis and optimization. Most of the works investigate a nearly-completed power grid at the post-layout stage, in which both the design (board, package and on-die grid) and the loading condition (logic circuit, excitation patterns) are well defined.…”

Section: Introductionmentioning

confidence: 99%

Early-Stage Power Grid Design

Zhuo

Gan

Shih

2014

Proceedings of the 51st Annual Design Automation Conference

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Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.

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