Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Jang, Sheng‐Lyang; Tang, Tz-Hua; Chen, Young-Shying; Sheu, Chorng-Jye

doi:10.1016/0038-1101(95)00414-9

Cited by 13 publications

(6 citation statements)

References 10 publications

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“…It is possible for both of these mechanisms to occur in p-FETs as well [49,50]. Under peak gate-current bias conditions, the shift in these devices is dominated by electron trapping in the oxide.…”

Section: Reliabilitymentioning

confidence: 96%

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

1999

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Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hotelectron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, highpressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (Q BD ), hot-electron degradation, and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.

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Section: Reliabilitymentioning

confidence: 96%

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

1999

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“…In p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs), the effect of channel shortening induced by oxide trapped electrons 1,2) is the main cause of device degradation. The oxide trapped electrons attract holes to the semiconductor surface and invert the channel from an nto a p-channel, this results in current enhancement and frequency shift of ring oscillator, and may play a fundamental limitation in the long-term reliability of very-largescale-integration/ultra-large-scale-integration (VLSI/ULSI) circuits.…”

Section: Introductionmentioning

confidence: 99%

Compact Hot-Electron Induced Oxide Trapping Charge and Post-Stress Drain Current Modeling for Buried-Channel p-Type Metal–Oxide–Semiconductor Field-Effect-Transistors

Sheu¹

2008

jjap

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In this paper, we present a complete and physics-based drain current model for hot-carrier damaged buried-channel (BC) ptype metal-oxide-semiconductor field-effect-transistors (pMOSFETs) operated in the forward and reverse-biased modes. Experimentally it was found that the post-stress drain current of BC pMOSFETs increases, this is caused by hot-carrierinduced electron trapping in the oxide. Considering the subthreshold operation, we present an complete electron gate current model and calculate the spatial distribution of oxide-trapping-charges by using an oxide trapping mechanism, and then we can model the hot-carrier damaged drain current by substituting the spatial distribution of oxide-trapping-charges into the damaged BC MOSFET drain current model. The damaged channel region due to the fixed oxide charges trapped during hotcarrier injection is treated as a bias and stress-time-dependent resistance. The degraded BC MOSFET drain current model is applicable for circuit simulation and its accuracy has been verified by experimental data.

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“…Therefore, the effective conducting length L E F F of the inversion layer in the undamaged region becomes shorter. The quasi 2-D analysis in the velocity saturation region within the undamaged region can be obtained from [2] and the length of channel length modulation LSAT can be solved as:…”

Section: At(rs T Rd)iimentioning

confidence: 99%

“…It has been recognized that not only nMOSFET's but also pMOSFET's are severely restricted by the hot-carrier induced damage. In nMOS-FET's the hot-carrier-induced interface states are the dominant factor for the degraded I-V characteristics [l], while in pMOSFET's the oxide-electron-trapping-induced channel shortening [2] is the main cause of device degradation, which results in current enhancement and frequency shift, and may play a fundamental limitation in the long-term reliability of VLSI/ULSI circuits [3]. Based on this channel shortening concept, Li et al [4] have developed a degraded pMOSFET model valid in the linear and saturation regimes for circuit reliability prediction.…”

Section: Introductionmentioning

confidence: 99%

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A Complete Asymmetric Drain Current Model For Post-stress Submicron pMOSFET's

Chen¹,

Jang²

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

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In this paper, we present a new, analytical and complete degraded drain current model for submicrometer PMOS-FET's. The model is valid in all operation regions. It can accurately describe the effect of the hot-carrier induced-trapped oxide charges on the device performance. The model is based on the channel shortening concept, it includes the effects of source/drain series resistances, the effective resistance of the hot-carrier damaged region, and the threshold voltage shift due to the oxide trapped charges. The model can describe the asymmetric post-stress drain currents in forward-and reverse-mode operation and can improve the accuracy of the prediction of drain current change after hot-carrier stress. It also can predict the time-dependence of degraded drain current with stress time under various stress conditions. The model can be empolyed in a circuit simulator to improve the accuracy of long-term circuit reliability simulation.

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Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Cited by 13 publications

References 10 publications

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

Compact Hot-Electron Induced Oxide Trapping Charge and Post-Stress Drain Current Modeling for Buried-Channel p-Type Metal–Oxide–Semiconductor Field-Effect-Transistors

A Complete Asymmetric Drain Current Model For Post-stress Submicron pMOSFET's

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