A Complete Asymmetric Drain Current Model For Post-stress Submicron pMOSFET's

Abstract

In this paper, we present a new, analytical and complete degraded drain current model for submicrometer PMOS-FET's. The model is valid in all operation regions. It can accurately describe the effect of the hot-carrier induced-trapped oxide charges on the device performance. The model is based on the channel shortening concept, it includes the effects of source/drain series resistances, the effective resistance of the hot-carrier damaged region, and the threshold voltage shift due to the oxide trapped charges. The model can describe the asymmetric post-stress drain currents in forward-and reverse-mode operation and can improve the accuracy of the prediction of drain current change after hot-carrier stress. It also can predict the time-dependence of degraded drain current with stress time under various stress conditions. The model can be empolyed in a circuit simulator to improve the accuracy of long-term circuit reliability simulation.