Minimizing pattern count for interconnect test under a ground bounce constraint

Marinissen, Erik Jan; Vermeulen, Bart; Hollmann, Henk D. L.; Bennetts, R.G.

doi:10.1109/mdt.2003.1188257

Cited by 22 publications

(6 citation statements)

References 5 publications

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“…TSV-based interconnects can be tested via dedicated test pattern generator structures to cover transition faults and shorts [112]. Though the number of interconnects is large, a few patterns can potentially test for all these faults.…”

Section: Mid-bond Post-bond and Final Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Mid-bond Post-bond and Final Testingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…Interconnect testing requires a dedicated interconnect test pattern generator, to cover for specific driver-receiver transition tests [30] as well as layout-independent shorts [31]. These algorithms detect all (hard) open and shorts through a set of digital test patterns that can be kept small, as it grows only logarithmically with the number of interconnects.…”

Section: Test Of Tsv-based Interconnectsmentioning

confidence: 99%

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D-and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D-and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.

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“…IEEE 1149.1 works through a narrow singlebit interface, as every JTAG terminal requires an additional chip pin and these are considered expensive. Fortunately, the prime focus of IEEE 1149.1 is PCB interconnect testing, and that requires only a small number of test patterns [25]. The single-bit interface pins are called tdi and tdo, and they transport both instructions and test data.…”

Section: Test Access Architecture For Pcbsmentioning

confidence: 99%

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

et al. 2011

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Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level.

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Minimizing pattern count for interconnect test under a ground bounce constraint

Cited by 22 publications

References 5 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

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