Minimal Energy Asynchronous Dynamic Adders

Obridko, I.; Ginosar, Ran

doi:10.1109/tvlsi.2006.884056

Cited by 6 publications

(3 citation statements)

References 24 publications

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“…Dynamic CMOS logic is a popular substitute for static CMOS logic [9]. Design with dynamic logic when speed is of primary importance.…”

Section: Introductionmentioning

confidence: 99%

Low power, less area, and highly efficient hybrid 1-bit full adder

Hemanth,

Sathish Kumar

2023

J. Phys.: Conf. Ser.

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The widely used and efficient technique is to design an FA circuit using XNOR-XOR cells in the Pass transistor and CMOS hybrid logic. The performance metrics of hybrid full adders, such as power, driving capability, and power, depend highly on the XNOR-XOR circuit. The proposed FA design provides optimization with respect to speed and performance. Low load capacitance and low static power dissipation in the circuit enabled the optimized design characteristics. The proposed circuits outperform existing designs in device parameters such as device speed, total energy consumption, power, and fanout. Cadence Virtuoso is the simulation tool used for simulations and results with a 90nm model. The test outcomes show the new design outperforms other FA designs regarding speed and power. In comparison to the available FA modules, the proposed FA reduces delay by 48% and improves power and power delay products by 7% and 52%, respectively. Microwind design software is used to create layouts. The paper presents a more straightforward layout of the proposed design that takes up less area.

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“…Dynamic CMOS logic is a popular substitute for static CMOS logic [9]. Design with dynamic logic when speed is of primary importance.…”

Section: Introductionmentioning

confidence: 99%

Low power, less area, and highly efficient hybrid 1-bit full adder

Hemanth,

Sathish Kumar

2023

J. Phys.: Conf. Ser.

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“…All the strategies above are synchronous methods, but asynchronous design is usually known as a powerful low power strategy because asynchronous computational blocks can be designed to consume energy only when and where needed [12]. Asynchronous strategies have been applied to so many low power designs [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27]. Several classic asynchronous low-power designs are briefly introduced in the following text.…”

Section: Introductionmentioning

confidence: 99%

Design of low-power low-area asynchronous iterative multiplier

You

Hei

Jia

et al. 2019

IEICE Electron. Express

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In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

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“…Full adder is most crucial component in arithmetic logic unit (ALU) which is used in computers, processors, communication devices, etc. Various design methods are adopted by researchers to design full adder circuits [1,2,3,4]. Shannon decomposition based technique [5] has been proposed for a power efficient full adder circuit.…”

Section: Introductionmentioning

confidence: 99%