Design of power efficient stable 1-bit full adder circuit

Subramaniam, S.; Singh, Ajay Kumar; Murthy, G. Ramana

doi:10.1587/elex.15.20180552

Cited by 3 publications

(1 citation statement)

References 10 publications

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“…Shahmini Subramanian, Ajay Kumar Singh and Gajula Ramana Murthy, 2018 [1] Proposed a stable 1 Bit Full Adder circuit, which provides better efficiency for power consumption. This paper describes the design of 14 Transistors based full adder stable circuit, which consume less power.…”

Section: Related Workmentioning

confidence: 99%

Deeper Insight of Various Full-Adder Designs with Various Techniques and Technology

Singh¹,

Sharma²,

Singh³

2019

IJRTE

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 Abstract: In this paper various type of full adder circuits with high speed operation have been analyzed. Power Consumption, Speed and Area are important factors of the design aspect of full adder circuit. Many researchers have worked on full adder designs using various technologies. Present paper deals with literature analysis based on full adder designs. , completed B.Tech in Electronics and communication from UPTU. I have two years industry experience in Central Electronics Limited. Currently pursuing M. Tech in VLSI system from Indira Gandhi Delhi Technical University for women, Delhi, India Ashiah Singh, , completed B.Tech in Electronics and communication from AKTU. M. Tech in Digital communication from RJIT, BSF Academy, India.

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Section: Related Workmentioning

confidence: 99%