Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node

Mushtaq, Umayia; Akram, M. W.; Prasad, Dinesh

doi:10.1080/1448837x.2022.2068468

Cited by 7 publications

(7 citation statements)

References 34 publications

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“…In the literature [25] layout of Conventional SG FinFET and INDEP FinFET based circuits is analyzed at 16 nm technology node using FinFET foundry with number of fins equal to one, fin thickness of 8 nm and fin height of 40 nm. The increase in area in case of FinFET INDEP technique is increased by 14%.…”

Section: Area Comparisonmentioning

confidence: 99%

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Mushtaq¹,

Akram²,

Prasad³

et al. 2022

Semicond. Sci. Technol.

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Due to the continuous downsizing of MOSFET (Metal Oxide Semi-conductor Field Effect Transistor) devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (Leakage Control Input DEPendent) is proposed for Nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various Short Gate (SG) FinFET logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71 % and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of PVT (Process Voltage and Temperature) variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68 % & 43.93% for PDP metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16nm technology node for FinFET logic devices using PTM model (Multigate BSIM-CMG) on HSPICE tool.

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Section: Area Comparisonmentioning

confidence: 99%

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Mushtaq¹,

Akram²,

Prasad³

et al. 2022

Semicond. Sci. Technol.

Self Cite

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“…Several techniques have presented in the literature related to SRAM cell for leakage power reduction. But the existing methods have several issues, like leakage current, read with write LPD, propagation delay, and degrade static noise margins 21–27 . These drawbacks have motivated to do this work.…”

Section: Introductionmentioning

confidence: 99%

“…These transistors are employed to diminish the leakage current. Finally, the performance of SGFinFETs‐SRAM‐LECTOR cell design is measured under area, read and write delay, read and write power, read and write speed, power delay product, stability analysis utilizing Static Noise Margin (SNM). The dependability examination is verified through activating Monte Carlo (MC) simulations for 500 samples through PVT parameters variation ±10% at TT process corner for the cases of hold, read, write. The simulation outcomes of Monte Carlo analysis are acquired with the help of HSPICE. The proposed technique is activated in HSPICE simulation tool. The efficiency of SGFinFETs‐SRAM‐LECTOR is compared with three existing methods, like FinFETs based SRAM cell design using self‐controllable voltage level, 21 FinFETs based SRAM cell design utilizing sleep transistor, drowsy cache, self‐controllable voltage modes, 22 FinFETs based SRAM cell design using input dependent technique 26 …”

Section: Introductionmentioning

confidence: 99%

“…But the existing methods have several issues, like leakage current, read with write LPD, propagation delay, and degrade static noise margins. [21][22][23][24][25][26][27] These drawbacks have motivated to do this work.…”

mentioning

confidence: 99%

“…The efficiency of SGFinFETs-SRAM-LECTOR is compared with three existing methods, like FinFETs based SRAM cell design using self-controllable voltage level, 21 FinFETs based SRAM cell design utilizing sleep transistor, drowsy cache, self-controllable voltage modes, 22 FinFETs based SRAM cell design using input dependent technique. 26 Continual manuscript is structured as follows: Section 2 delimits recent studies, Section 3 illustrates about the proposed method, Section 4 displays the outcomes, Section 5 concluding this manuscript.…”

mentioning

confidence: 99%

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Designing power‐efficient SRAM cells with SGFinFETs using LECTOR technique

Sankranti,

Roji Marjorie

2023

Softw Pract Exp

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Static random‐access memory (SRAM) plays a vital component of digital systems. The main issue of SRAM cells is power leakage, which results in an increase in chip area. Therefore this manuscript proposes a shorted‐gate fin‐type field‐effect transistor based SRAM cell utilizing leakage control transistor technique (SGFinFETs‐SRAM‐LECTOR) for decreasing the leakage power delay by improving the static noise margins (SNMs) together with power delay product (PDP). Here, the SGFinFETs‐SRAM‐LECTOR is primarily applied to stacking enhancement for lessening the leakage power dissipation (LPD). Two more transistors are used in LECTOR for reducing the leakage current with delay, which is based on transistor stacking. LECTOR employs two more transistors that are connected in series between pull‐up and pull‐down networks that means additional SG FinFETs PMOS transistor insertions amongst the pull‐up network and output terminal, additional SG FinFETs NMOS transistor insertions amidst the pull down network and output terminal. These additional transistors can decrease the leakage current. The simulation of the proposed approach is implemented in HSPICE simulation tool. Some metrics are computed to validate the efficacy of the proposed approach. Finally, the proposed technique reaches 11.31%, 51.47%, 45.46% less read delay, 44.44%, 26.33%, 33.45% less write delay, 36.12%, 45.28%, 26.45% less read power, 34.5%, 33.56%, 22.41% less write power, 37.4%, 15.3%, 26.54% high read SNM, 33.67%, 35.8%,12.09% high write SNM when analyzed to the existing models.

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