Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing

Chow, K.; Abercrombie, David; Basel, M.

doi:10.1109/socc.2006.283855

Cited by 5 publications

(3 citation statements)

References 2 publications

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“…Due to currents flowing in both directions inside signal wires, the current average is null. Therefore signal network is assumed relatively safe toward EM phenomenon [4,5].…”

Section: Electromigration Degradation Mechanism In Power Gridmentioning

confidence: 99%

Redundancy method to assess electromigration lifetime in power Grid design

Ouattara¹,

Doyen²,

Ney³

et al. 2013

2013 IEEE International Interconnect Technology Conference - IITC

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The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

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“…Due to currents flowing in both directions inside signal wires, the current average is null. Therefore signal network is assumed relatively safe toward EM phenomenon [4,5].…”

Section: Electromigration Degradation Mechanism In Power Gridmentioning

confidence: 99%

Redundancy method to assess electromigration lifetime in power Grid design

Ouattara¹,

Doyen²,

Ney³

et al. 2013

2013 IEEE International Interconnect Technology Conference - IITC

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“…Input test patterns are applied to DUTs and output responses are then observed and compared with reference values corresponding to fault-free operation [24]. Non-destructive techniques include a) low frequency noise measurement and b) in-situ high resolution resistometric measurement [25].…”

Section: Background and Motivationmentioning

confidence: 99%

On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements

Suresh

Vijayakumar

Kundu

2011

2011 IEEE Computer Society Annual Symposium on VLSI

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Current printability issues can be attributed to subwavelength lithography and its sensitivity to manufacturing process variations. Resulting process variations cause performance, yield and reliability problems. As noted in ITRS, conventional burn-in test is losing cost-effectiveness in reliability screening. In this paper, we use lithography process corner information in reliability screening. The lithographic process corner information is decoded from circuit measurements using a tester. We propose two methodologies for binning of dies based on Mean Time to Failure (MTTF). Lithography aware LUT based binning uses pre-estimated MTTF values to bin dies based on the detected litho-process corner. Lithography aware pattern based binning uses test patterns specific to litho-process corner along with existing techniques like burn-in test or Electrical Linewidth Metrology (ELM). Accurate determination of die level process corner is an important step employed in the proposed methodology. This work aims at: a) test Pattern generation for increased reliability test coverage incorporating manufacturing variations, b) utilization of die based process corner information for choosing the best test pattern set for improved fault coverage, c) achieving acceleration of infant mortality within the manufacturing test flow, and d) die-level determination of MTTF incorporating lithography process variation and hencedecreasing the binning-yield loss. Experiments on ISCAS'85 circuits for varying exposure dose and de-focus values show an average variation of 20-30nm in interconnect widths, resulting in a deviation of as much as 40% in the estimated MTTF. It is also observed that, for maximum fault coverage, the test vector set changes in size and pattern across various process corners.

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“…The electromigration (EMG) phenomenon is becoming more and more critical for chip reliability since the 32 nm technology node [1][2][3]. In order to anticipate this reliability issue, EMG checks are done at design level based mainly on the electrical parameters [4].…”

Section: Introductionmentioning

confidence: 99%