Redundancy method to assess electromigration lifetime in power Grid design

Abstract

The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration

“…However, EMG degradation mechanisms depend also on the wire topological parameters and the interconnection network configuration. In a previous work [5] it was shown that redundant paths exist in power grid networks. These paths can take over from a power supply presenting an EMG failure and thus allow the chip to operate.…”

Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling

“…voltage scaling (AVS) [8]. To meet lifetime requirements, design teams overcome mean time to failure (MTTF) with respect to EM-induced interconnect voids and shorts by applying design guardbands [19] [l3] [24] [21]. Sometimes, design teams can try to make interconnects 'immortal' by limiting segment lengths to be less than or equal to the Blech length [7].…”

“…Furthermore, [28] [38] [36]. As technology advances, more physical design factors such as temperature [10], process variation [24], and growing dominance of BTl and AVS must be considered in order to achieve accurate EM evaluation and signoff. (c) Physical design approaches for EM-durable circuits.…”