Mechanical Stress and Defect Formation in Device Processing

Abstract

In this work we address the problem of estimating the mechanical stress and the related risk of crystal defect generation in a complex device process. The validity of numerical calculations of the mechanical stress developed in the device process flow is assessed by comparing the simulation results with the electrical measurements of test structures designed to monitor the dislocations formation and of other silicon strain sensitive structures. The results show that based upon numerical calculations it is possible to define mechanical stress criteria for preventing defect generation. By using this sort of criteria, potentially dangerous process variations can be easily identified. This method is quite general and can be applied to any device process flow. On the other hand, by comparing the electrical results of structures prone to defect generation and of stress-sensitive transistors with a non-critical geometry for defect generation, it is shown that after defect nucleation the elastic stress in non-critical structures and the defect-related failure fraction in critical structures may evolve into opposite directions. Therefore, suitable stress criteria are needed at all the levels in the process flow where crystal damage may cause defect nucleation. In this study it is also pointed out that a high temperature stress release annealing can be beneficial for stress reduction and defect prevention, but its position in the process flow is critical.

High Doping Density/High Electric Field, Stress and Heterojunction Effects on the Characteristics of CMOS Compatible p-n Junctions

“…due to the volume expansion of SiO 2 compared with Si, thermal stresses, created during fast cooling of the wafers after field oxidation 90 were shown to play an important role. In many cases, the stress was high enough to exceed the yield stress of silicon, leading thus to the creation of extended defects, [94][95][96][97][98][99] which were penetrating the depletion region and, hence, cause a reduction of the generation lifetime s g in Eq. 1.…”

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

“…As previously mentioned, in process flows with a STI structure the mechanical stress is developed during the thermal oxidations that follow the STI formation (8). In addition, the deeper the trench, the higher the stress-related dislocation formation probability is (17). Numerical simulations showed that the silicon compression is maximum at the top corner of the active area.…”

“…Electrical measurements. Dislocations in transistors are electrically active if they connect the source and the drain regions (8,10,17,21). In this case, the dislocation usually acts as a source-to-drain conductive path, because of the anomalous dopant diffusion from the source and drain regions along the dislocation.…”

“…To this aim, the stress components were averaged over a region close to the surface. Defect formation most frequently takes place in the recristallization of highly stressed regions (10,12,17), so the stress values in the region damaged by the implantation are crucial for defect formation. Therefore we chose to average the stress components over a depth roughly corresponding to the depth of the amorphous region produced by arsenic high dose implantation used for the source and drain formation.…”