(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

Abstract

This paper collects the results of some experiments aimed at investigating the physical mechanisms of defect generation in devices. It is shown that suitable limits for the mechanical stress can be defined to prevent defect generation. In addition, a high temperature stress release annealing can be beneficial for stress reduction and defect prevention. The annealing of implanted layers may result in crystal defect formation even with no contribution from mechanical stress. In this case, the silicon surface plays a relevant role in reducing the point defect concentration and hence the nucleation of extended defects. In the annealing process of high energy implantations, the most damaged region is far from the wafer surface. Under these conditions, impurities in the silicon substrate play a relevant role in determining the resulting defect morphology. The presence of interstitial oxygen forces defects to grow along <110> directions parallel to the silicon surface, thus preventing them to reach the device region.

Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations

“…This can be attributed to the severely damaged lattice within the P+ source regions. As observed in Table IV, the variation within the '5x RT Box' condition is ~6x greater than the low damage devices which is evident of random defects limiting current flow [6,12]. Although, this damaged lattice is still observed within the 'MSHB 5x RT' and 'HSMB 9x RT' implanted devices, the overall damage suffered is much less, and has minimal effects on 3 rd Quadrant performances.…”

(Invited) Single Dislocations as Nanostructure Devices: Physics and Applications

“…The review, given in 1999, emphasizes the detrimental and the beneficial role of crystal defects in silicon. The detrimental role of defects on device performance was studied by numerous authors until now because increasing the wafer size and simultaneously decreasing feature size, mostly combined with novel processing techniques, introduce new crystal defect phenomena (2)(3)(4). On the other hand, the beneficial side of crystal defects is of increasing importance.…”

Impact of Defect‐Induced Strain on Device Properties

“…[1,2] Further, scaling combined with novel processing techniques, however, introduce new crystal defect phenomena [3,4] An individual defect, for instance, may already cause device failures by decreasing feature size below 20 nm. Therefore, numerous comprehensive strategies were developed to avoid growthand process-induced defects such as point defects, dislocations, grain boundaries, and precipitates.…”