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We have investigated the effects of deliberate heavy metals contamination on dark current and image defects in CMOS Image Sensors (CIS). Analysis of dark current in these imager dice has revealed different behaviors among most important 3d metals present in the process line. We have implanted directly in 3 Mega array pixels the following metals: Cr, V, Cu, Ni, Fe, Ti, Mo, W, Al and Zn. Analyzing the dark current "spectrum" as obtained for fixed integration periods of time by means of standard image-testing equipment, these impurities can be identified and detected with a sensitivity of ∼ 10 9 traps/cm 3 or higher.

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Various procedures for heavy metal gettering in silicon p-n junctions have been compared in order to test the effectiveness of dopants and extended defects as getter sites; the role of silicon interstitials in the gettering process has also been studied. It has been found that only phosphorus and boron atoms are effective getter sites, while arsenic and antimony are not; such gettering effectiveness is independent of the presence of extended defects in the heavily doped regions. During a moderate temperature annealing (segregation annealing) dissolved metal impurities diffuse from the space-charge region of the devices and segregate at getter sites. Extended defects generated by oxygen precipitation and stacking fault backside damage have some ability to capture metal impurities, but electrical tests show that they do not provide a satisfactory gettering technique. The role of self-interstitials consists of increasing the dissolution rate of metal precipitates with subcritical radii, so that the segregation of metal impurities into getter sites is made easier; however, a complete gettering process requires three steps, that is: (1) the creation of effective getter sites; (2) the dissolution of metal precipitates; (3) the segregation of dissolved metal impurities at getter sites. Some of these steps may be activated simultaneously.

Camera-based thermoreflectance microscopy is a unique tool for high spatial resolution thermal imaging of working integrated circuits. However, a calibration is necessary to obtain quantitative temperatures on the complex surface of integrated circuits. The spatial and temperature resolutions reached by thermoreflectance are excellent (360 nm and 2.5 × 10−2 K in 1 min here), but the precision is more difficult to assess, notably due to the lack of comparable thermal techniques at submicron scales. We propose here a Peltier element control of the whole package temperature in order to obtain calibration coefficients simultaneously on several materials visible on the surface of the circuit. Under high magnifications, movements associated with thermal expansion are corrected using a piezo electric displacement and a software image shift. This calibration method has been validated by comparison with temperatures measured using integrated thermistors and diodes and by a finite volume simulation. We show that thermoreflectance measurements agree within a precision of ±2.3% with the on-chip sensors measurements. The diode temperature is found to underestimate the actual temperature of the active area by almost 70% due to the thermal contact of the diode with the substrate, acting as a heat sink.

In this paper, the correlation between dislocation density and transistor leakage current is demonstrated. The stress evolution and the generation of defects are studied as a function of the process step, and experimental evidence is given of the role of structure geometry in determining the stress level and hence defect formation. Finally, the role of high-dose implantations and the related silicon amorphization and recrystallization is investigated.

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