High Doping Density/High Electric Field, Stress and Heterojunction Effects on the Characteristics of CMOS Compatible p-n Junctions

Abstract

This paper critically reviews the different mechanisms impacting the current-voltage and capacitance voltage characteristics of complementary metal oxide semiconductor (CMOS) compatible p-n junctions. Special attention is given to the influence of high doping density=high electric fields, mechanical stress and the presence of a hetero-junction either at the junction or in the depletion region. The basic mechanisms reported in the literature are checked for their validity for state-of-the-art structures and processing techniques. Critical issues are pointed out and illustrated for advanced CMOS compatible hetero-junctions, where high-field effects, like trap-assisted tunneling (TAT) and band-to-band-tunneling (BTBT) play a prominent role. The presence of an isotype hetero-junction gives rise to frequency dispersion in the depletion layer capacitance, which becomes more pronounced in combination with grown-in or processing-induced defects at the hetero-interface. Finally, the challenges and opportunities for future devices are addressed.

Bandlike and localized states of extended defects in n-type In0.53Ga0.47As

“…As shown in Fig. 4, the buffer layer tilt about 1°only in the [1][2][3][4][5][6][7][8][9][10] direction, as already discussed for similar cases in the literature, [24][25][26] comes from the different gliding mobility between α and β 60°dislocations. Generally speaking, G_SRB is compressively stressed during the strained buffer layer growth.…”

“…Thus, the orientation of the dislocation line at the (001) interface will change as well: 17 (i) under tensile stress, α type yields a misfit dislocation (MD) line in the [1][2][3][4][5][6][7][8][9][10] direction and β type in [110]. (ii) Under compressive stress, α type results in a [110] MD line and β type in [1][2][3][4][5][6][7][8][9][10]. In addition, it is well known that a 60°dislocation is dissociated into a 30°and a 90°Shockley partial dislocation to glide efficiently, as reported in detail by Marée et al 19 Since this movement is energetically unfavorable for the shuffle set of dislocations, 18,20 it is generally believed that mobile 60°dislocations belong to the glide set.…”

“…For sample P_In47 and P_In40, as mentioned in the paragraph on layer strain, the n+ In x Ga 1-x As/substrate interface is under tensile strain and the subsequent lattice-matched is at the p/n− layer. Under this situation, the cross-hatch lines (white dashed lines) located in the [1][2][3][4][5][6][7][8][9][10] direction are thought to correspond with α dislocation MD lines with As (g) core atoms and predominant in both P_In47 and P_In40. Beside α dislocations, sample P_In40 also exhibits a small number of β dislocation MD lines (white dashed lines located in [110] direction) and additional defects called "micro-crack" (dark grooves located in [110] direction), in agreement with literature data for the tensile stressed In 1-x Ga x As/InP system.…”

“…3 However, these methods inevitably lead to extended defects during the heteroepitaxial growth, because of lattice and thermal mismatch. For example, defects lying in the (111) plane cannot be trapped by the shallow trench isolation (STI) sidewalls in the (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11) plane. This is one of the major issues in InGaAs-based devices.…”

Low-Frequency Noise Assessment of Different Ge pFinFET STI Processes

“…However, heteroepitaxy on a Si substrate may be prone to extensive defect generation, mainly misfit dislocation and threading dislocation (TD) [6], since there is a mismatch in lattice parameter and coefficient of thermal expansion between Si and Ge [7]. Moreover, the TD density is a key parameter to be reduced, since it strongly affects the device performance [8], [9].…”