Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

D. Placencia et al. report on the creation of organic photovoltaic cells from textured titanyl phthalocyanine (TiOPc) heterojunctions. The foreground of this frontispiece shows the crystal structures of the two polymorphs of TiOPc used, along with FE‐SEM images of TiOPc on an ITO electrode before (left), and after (right) phase transformation of the TiOPc film. The background shows AFM phase images of the two TiOPc polymorph films, showing the dewetting of the surface and the nanotexturing which occurs during the solvent annealing/phase transformation process.

The impact of different process parameters, namely, the trench etch depth, the total epitaxial SiGe thickness, and the epi elevation, on the leakage current of recessed Si 0.8 Ge 0.2 source/drain junctions has been systematically investigated. Besides the behavior of the forward and the reverse currents, attention is also given to the temperature dependence of the leakage current. It is found that both the bulk and the peripheral leakage current density increase strongly with increasing etch depth. Empirically, an exponential dependence has been observed between the area leakage current density at Ϫ1 V and the distance d j between the Si 0.8 Ge 0.2 -Si interface and the electrical p-n junction, whereby an increase by 1 dec for every 43 nm of reduction in d j occurs. This can be understood by the fact that the responsible defects originate mainly at the SiGe-Si interface. The perimeter current density shows for certain process splits an exponential dependence on the total thickness of the epitaxial layer t SiGe , with an increase by a decade for every 50 nm increase in thickness. Also, the generation and recombination lifetimes have been studied in order to determine an effective energy level of the electrically active defects.