MA BE-SONOS: A Bandgap Engineered SONOS using Metal Gate and Al2O3 Blocking Layer to Overcome Erase Saturation

Lai, Sheng-Chih; Lue, Hang-Ting; Yang, Ming-Jui; Hsieh, Jung-Yu; Wang, Szu-Yu; Wu, Tai–Bor; Luo, Guang-Li; Chien, Chao-Hsin; Lai, Erh-Kun; Hsieh, Kuang-Yeu; Liu, R.; Lu, Chin-Yuan

doi:10.1109/nvsmw.2007.4290593

Cited by 21 publications

(11 citation statements)

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“…BE-SONOS may also be combined with high-K top dielectric and form a BE-MANOS device [11]. Again, the thick non-optimized high-K Al 2 O 3 also causes additional reliability problems thus we find that the best way to improve the reliability is to insert a sufficiently thick buffer oxide in between Al 2 O 3 and SiN, and also minimize the high-K thickness to reduce the bulk trapped charges.…”

Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 92%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

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Section: Planar 2d Charge-trapping (Ct) Devicesmentioning

confidence: 92%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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“…This drawback can be overcome by using either a high-K IPD material [17,[67][68][69][70] or a charge-trapping device instead of an FG device. [71][72][73][74][75][76] The high-K IPD materials enable a high GCR without the requirement for a wrap structure. However, most high-K IPD materials with high GCR value generally exhibit a low bandgap, which is not suitable for flash memory because of its susceptibility to the gate injection.…”

Section: Electrical Scaling Challengingmentioning

confidence: 99%

“…The substrate hole may directly tunnel into the nitride layer under a low electric field that is induced by the storage charge to neutralize the electrons, thus impairing the data retention. Hence, to mitigate the performance of SONOS, a set of new nitride storage devices with more reliable performance, such as TaN/Al 2 O 3 /SiN/SiO 2 /Si (TANOS), [72] bandgap engineering SONOS (BE-SONOS), [73] BE-metal/ Al 2 O 3 /SiN/SiO 2 /Si (BE-MANOS), [74,75] [74,75] and BE-charge Electron. Mater.…”

Section: Electrical Scaling Challengingmentioning

confidence: 99%

Physical principles and current status of emerging non-volatile solid state memories

Wang

Yang

Wen

2015

Electron. Mater. Lett.

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Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance.

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“…One method is to apply the charge-trapping flash (CTF) memory such as the silicon-oxide-nitride-oxide-silicon (SONOS) structure, which has been discovered by Wegener in 1967 [5]. The performance can be further enhanced by using the bandgap-engineered SONOS (BE-SONOS), where the multiple tunneling layers, SiO 2 /Si 3 N 4 /SiO 2 (ONO), have been implemented [7][8][9][10]. The charge loss can be reduced due to the thick ONO tunneling layers, while the carrier injection efficiency can be kept as the conventional SONOS flash memory by using the band engineering technique.…”

Section: Introductionmentioning

confidence: 99%