State-of-the-art flash memory devices and post-flash emerging memories

Abstract

Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

Modulating the Performance of MoS2-Based Nanocrystal Memory via Ag Ion Implantation

“…Many research studies have proven that metal nanocrystals (e.g., Ag, Au, etc.) can be formed directly in silicon and silicon dioxide by ion implantation. − Also, for nitride-based charge trap memory with SiO 2 /Si 3 N 4 /SiO 2 storage structure, Si 3 N 4 has a work function of 4.9 eV, and the deeply trapped electrons are not easily detrapped during erasing . Conversely, silver has a work function of 4.26 eV, which can form a suitable trap level that is neither too deep to affect the operating speed nor too shallow to cause charge leakage.…”

“…17 erasing. 20 Conversely, silver has a work function of 4.26 eV, which can form a suitable trap level that is neither too deep to affect the operating speed nor too shallow to cause charge leakage. Therefore, Ag nanocrystals can be embedded into SiO 2 at a certain depth and act as a charge trap layer by controlling the ion dose and energy precisely.…”

A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory

“…Under this trend, charge trapping (CT) flash memory technology has long been investigated and proposed as the most promising candidate within its domain due to its immunity to stress-induced leakage current and reduced coupling capacitance. As such, this technology has thus been recently attracting considerably more attention since it is ideally suitable for three-dimensional (3-D) vertical architectures which exploits the third dimension of the devices to fulfil the ever-increasing demand for bit cost [1][2][3][4][5][6][7][8]. 3-D CT NAND flash is also forecasted to continue the trend of scaling NAND flash below the 15 nm technology node [9].…”

Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology

“…Although SONOS devices are more radiation-tolerant than FG memories, only limited work has been published on their radiation tolerance to date, because they suffer from other limitations, such as low memory density and their need for balance between memory retention and erase speed [9][10][11]. However, interest in SONOS memory cells has recently been renewed by new architectures such as three-dimensional (3D) SONOS and nitride-read-only-memory (NROM) [10][11][12], which circumvent most of the limitations of these memories.…”