NAND Flash memory has scaled at phenomenal speed in the last decade and conventional floating gate (FG) Flash memory has now commenced volume production in the 2X nm node. Despite this stunning success, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (Multi-level Cell, or more than one bit storage per cell) storage. The simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels) also make CT suitable for 3D stacking. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1X nm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as TANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues.

In this paper, bottom-oxide thickness (T bo ) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor. Index Terms-Oxide thickness, positive oxide charge-assisted tunneling, Shockley-Read-Hall (SRH) rate equation, SONOS retention mechanisms.

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