A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET

Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application

“…The increase in V TH with reduction in channel diameter is a result of deep depletion in narrow wires. Indeed, the potential drop across the cylindrical nanowire increases quadratically with the nanowire radius and gives an increasing negative contribution to the threshold voltage [5][6]. The slight increase in drain current with increasing negative gate voltage is a result of the band-to-band tunneling resulting from the large electrical field across the floating body/drain junction [7].…”

On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories

“…The impact of trapped charges on the Id(Vg) transfer characteristics has been studied (figure 1b). We see that, during a write step, the charge trapping over the fin corners is strongly enhanced due to the electric field enhancement [1,3]. The smaller the curvature radius (R C ) is, the bigger and faster will be the charge trapping.…”

Barrier engineering in metal–aluminum oxide–nitride–oxide–silicon (MANOS) flash memory: Invited

“…In addition, the gate-side electron injection results in erase saturation. To overcome this problem, a barrier engineering (BE) technique has been proposed for both the tunneling oxide and blocking layer/gate electrodes [10,11,14,[17][18][19][20]22]. To use BE in CTF flash devices, the key design considerations are (1) a gate work function for mitigating gate injection and a faster eraser speed, (2) a high-k blocking layer to enable a lower equivalent oxide thickness (EOT) and low voltage operation, (3) a charge trap layer for effective trapping and multi-states, and (4) tunnel oxide for a trade-off between a faster eraser and good retention.…”

“…In a conventional floating gate NAND, both the program and erase operations are performed by electron tunneling to and from the floating gate, respectively. In a TANOS-type CTF, however, the erase operation mainly occurs through holes tunneling from the substrate [14,[18][19][20][21]. Due to its greater hole-barrier, the erase speed in CTF is slower than that of the floating gate.…”