Junction-Less Stackable SONOS Memory Realized on Vertical-Si-Nanowire for 3-D Application

Abstract

This study presents vertical Si-nanowire (SiNW) gateall-around (GAA) non-volatile memory with channel diameter down to 20nm. The junction-less devices with SiN trap layer is found to have comparable memory characteristics (3.2V in 1ms P/E at +15V/-16V) to the junction-based cell. Despite of that, the absence of junctions reduces the process complexity and makes vertical SiNW a suitable platform for multi-level stacked ultra high density memory application. Keywords-Junction-less (JL), Gate-all-around (GAA), 3-D flash memory, vertical silicon nanowire (SiNW).I.

Enabling Ultrahigh-Aspect-Ratio Silicon Nanowires Using Precise Experiments for Detecting the Onset of Collapse

“…This, coupled with the ubiquitous use of silicon in the semiconductor industry, make Si NWs ideal for commercial applications. Increasing the surface area of the nanowires–by both increasing the aspect ratio and increasing the cross-section perimeter–can enable higher-performance transistors, , memory devices, , sensors, − capacitors, , and batteries. , Si NW arrays with vertical sidewalls and precise spacing between NWs can also be used in microfluidics applications, such as Nano-DLD arrays, to filter sub-50-nm biological species such as exosomes and antibodies . However, high-aspect-ratio Si NWs are prone to clustering and collapse, − because of adhesion and capillary forces, which decreases the yield and performance in the above applications.…”