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The scaling down of the technology node makes integrated circuits more susceptible to soft errors, normally caused by radiation strike. In this paper, we propose a novel Soft Error Immunity (SEI) SRAM cell using a standard 65nm CMOS process, which has good tolerance to soft errors, especially at read state. SPICE simulation results show that the proposed cell is robust to the variation of process, voltage and temperature. Extensive 3-D technology computer-aided design (TCAD) simulation analyses show that the proposed cell can recover the upset-state. Index Terms-soft error upset (SEU), soft error immunity (SEI), SRAM

In this paper, we have studied the total ionizing dose (TID) radiation response up to 2 Mrad(Si) of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells and memory circuits, fabricated in a 130 nm complimentary metal-oxide-semiconductor (CMOS) SONOS technology. We explored the threshold voltage (V T) degradation mechanism and found that the V T shifts of SONOS cells depend on the charge state; simply programming the cell to a higher V T cannot compensate for the radiation induced V T loss. The off-state current (I off) increase in the SONOS cell is also studied in this paper. Both V T and I off degradation would affect the memory system. Read data failures are mainly caused by V T shifts under irradiation, and program and erase failures are mainly caused by increased I off , which overloads the charge pumping circuit. By varying the reference current, our 4 Mb NOR flash chip has the potential to survive a radiation dose of 1 Mrad(Si) in read mode.

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A novel internal electric field enhanced retention model for localized charge trapping memory devices is proposed to explain the reliability degradation. According to the model, the excitation energy level distribution profiles of trapped holes after different P/E cycling stress are demonstrated for the first time.

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the total ionizing dose (TID) radiation response of a flash memory circuit including high voltage (HV) periphery was studied. We show that functional failure of the charge pumps (CP) is mostly caused by an increased load current, due to radiation induced leakage current in the HV pass transistors. This leads to a failure to program/erase the array in turn.