Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology

Qiao, Fengying; Pan, Liyang; Xiao, Yu; Ma, Hui; Wu, Dong; Xu, Jun

doi:10.1007/s11432-013-4982-7

Cited by 10 publications

(3 citation statements)

References 19 publications

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“…With the intensive application of data storage in emerging technologies, 3-D NAND flash memory technology has been considered as a promising candidate for future memory solutions [1][2][3][4][5]. This is because it overcomes many challenges faced by conventional planar (2-D) NAND flash memory [6,7] and meets the requirements for mass storage devices [8].…”

Section: Introductionmentioning

confidence: 99%

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Wang

Lun

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a simulation method to model the program Vth distribution of 3-D vertical channel TLC/QLC charge-trapping NAND flash memory. The program Vth distribution can be calculated by considering ISPP noise, WL-WL interference, and the RTN effect of tunneling oxide and poly Si, which are the major physical factors affecting the width of program Vth distribution. Then, the program Vth distribution shapes with different ISPP incremental voltage steps are compared, and the results are found to be consistent with the experimental results. Code and layer-dependent coupling coefficients of WL-WL interference in 3-D vertical channel NAND flash memory are considered. The effect of RTN on the program Vth distribution is comprehensively studied. The program Vth distribution of a WL is calibrated with the measurement, and a good agreement is obtained, validating the array program Vth distribution simulation method. The simulation method can help in improving the reliability of 3-D TLC NAND flash memory and provides guidance for the design and optimization of 3-D QLC NAND flash memory technology.

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Section: Introductionmentioning

confidence: 99%

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Wang

Lun

et al. 2019

Sci. China Inf. Sci.

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“…Owing to the rapid improvement of process technology, the density and performance of flash memory have been improved greatly with flash cell size scaling [1][2][3][4]. Low cost, high density, low power and short-latency memory for large system are the main demands of modern memory design.…”

Section: Introductionmentioning

confidence: 99%

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

Liu

et al. 2015

Sci. China Inf. Sci.

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A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply. CitationLiu L F, Wu D, Liu X M, et al. A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time.

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“…With little tuning effort other commercial SONOS cells might be used for the experiment. Common SONOS devices exhibit very thin layers of the ONO gate stack, with approximate thickness of 2 nm for the tunnel oxide (O), 5-10 nm for the nitride layer (N) and 5 nm for the blocking oxide (O) towards the gate electrode [22,23]. Their fabrication is reliably performed with a 180 nm technology node and smaller.…”

mentioning

confidence: 99%

Memristive device based on a depletion-type SONOS field effect transistor

Himmel

Ziegler

Mähne

et al. 2017

Semicond. Sci. Technol.

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State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON /R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

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Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology

Cited by 10 publications

References 19 publications

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Modeling of program Vth distribution for 3-D TLC NAND flash memory

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

Memristive device based on a depletion-type SONOS field effect transistor

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