LV&lt;sup&gt;&amp;#x2217;&lt;/sup&gt;: A low complexity lazy versioning HTM infrastructure

IEEE Trans. Parallel Distrib. Syst.

Acacio

Garcia

2013

The efficient management of conflicts among concurrent transactions constitutes a key aspect that hardware transactional memory (HTM) systems must achieve. Scalable HTM proposals so far inherit the cache-based style of conflict detection typically found in bus-based systems, largely unaware of the interactions between transactions and directory coherence. In this paper, we demonstrate that the traditional approach of detecting conflicts at the private cache levels is inefficient when used in the context of a directory protocol. We find that the use of the directory as a mere router of coherence requests restricts the throughput of conflict detection, and show how it becomes a bottleneck under high contention. This paper proposes a scheme for conflict detection that decouples conflict detection from cache coherence in order to overcome pathological situations that degrade the performance of an eager HTM system. Our scheme places bookkeeping metadata at the directory, introducing it as a separate hardware module that leaves the coherence protocol unmodified. In comparison to a state-of-the-art eager HTM system, our design handles contention more efficiently, minimizes the performance degradation of false positives for signatures of similar hardware cost, and reduces the network traffic generated.

Section: Reducing False Positives Of Signaturesmentioning

confidence: 99%

“…To retain isolation on overflowed lines, cache controllers need a way of determining if an address whose tag is not found in cache indeed belongs to the read and write sets of its transaction. The solution can range from a single overflow bit [16], to an overflow signature [18] or a permissions-only cache [2].…”

Section: Background and Related Workmentioning

confidence: 99%

Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory

IEEE Trans. Parallel Distrib. Syst.

Acacio

Garcia

2013

“…For this evaluation, we have selected seven (out of eight) transactional applications from the STAMP suite [2]: genome, intruder, kmeans, labyrinth, ssca2, vacation and yada. The application, bayes, was excluded since it exhibits unpredictable behaviour and high variability in its execution time [6], [13]. For kmeans and vacation, both high and low contention configurations were used.…”

Section: A Experimental Setupmentioning

confidence: 99%

“…Tomic et al [17] describe an eager conflict detection design that commits transactions lazily, utilizing directory coherence in MESI based systems with two levels of private caching. Negi et al developed a broadcast-based lazy commit protocol in [13] that eliminates the need for write-backs or cache-line invalidation messaging at commit.…”

Section: Related Workmentioning

confidence: 99%

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory

Negi

2011 International Conference on Parallel Processing

Acacio

et al. 2011

Self Cite

Abstract-Hardware transactional memory (HTM) systems have been studied extensively along the dimensions of speculative versioning and contention management policies. The relative performance of several designs policies has been discussed at length in prior work within the framework of scalable chipmultiprocessing systems. Yet, the impact of simple structural optimizations like write-buffering has not been investigated and performance deviations due to the presence or absence of these optimizations remains unclear. This lack of insight into the effective use and impact of these interfacial structures between the processor core and the coherent memory hierarchy forms the crux of the problem we study in this paper. Through detailed modeling of various write-buffering configurations we show that they play a major role in determining the overall performance of a practical HTM system. Our study of both eager and lazy conflict resolution mechanisms in a scalable parallel architecture notes a remarkable convergence of the performance of these two diametrically opposite design points when write buffers are introduced and used well to support the common case. Mitigation of redundant actions, fewer invalidations on abort, latency-hiding and prefetch effects contribute towards reducing execution times for transactions. Shorter transaction durations also imply a lower contention probability, thereby amplifying gains even further. The insights, related to the interplay between buffering mechanisms, system policies and workload characteristics, contained in this paper clearly distinguish gains in performance to be had from write-buffering from those that can be ascribed to HTM policy. We believe that this information would facilitate sound design decisions when incorporating HTMs into parallel architectures.

“…The second generation of HTM implementations focused particularly on conflict detection and resolution policies by adopting flexible mechanisms such as detecting write-write conflicts eagerly and read-write conflicts lazily [26], detecting all conflicts eagerly and resolving them lazily [28], and providing the flexibility of detecting and resolving conflicts either eagerly or lazily, depending on the application [21]. In this paper, we focus on version management, the third key HTM design dimension.…”

Section: Introductionmentioning

confidence: 99%

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Armejach

Seyedi

2011 International Conference on Parallel Architectures and Compilation Techniques

et al. 2011

Abstract-Transactional Memory (TM) potentially simplifies parallel programming by providing atomicity and isolation for executed transactions. One of the key mechanisms to provide such properties is version management, which defines where and how transactional updates (new values) are stored. Version management can be implemented either eagerly or lazily. In Hardware Transactional Memory (HTM) implementations, eager version management puts new values in-place and old values are kept in a software log, while lazy version management stores new values in hardware buffers keeping old values in-place. Current HTM implementations, for both eager and lazy version management schemes, suffer from performance penalties due to the inability to handle two versions of the same logical data efficiently.In this paper, we introduce a reconfigurable L1 data cache architecture that has two execution modes: a 64KB general purpose mode and a 32KB TM mode which is able to manage two versions of the same logical data. The latter allows to handle old and new transactional values within the cache simultaneously when executing transactional workloads. We explain in detail the architectural design and internals of this Reconfigurable Data Cache (RDC), as well as the supported operations that allow to efficiently solve existing version management problems. We describe how the RDC can support both eager and lazy HTM systems, and we present two RDC-HTM designs. Our evaluation shows that the Eager-RDC-HTM and Lazy-RDC-HTM systems achieve 1.36× and 1.18× speedup, respectively, over state-of-theart proposals. We also evaluate the area and energy effects of our proposal, and we find that RDC designs are 1.92× and 1.38× more energy-delay efficient compared to baseline HTM systems, with less than 0.3% area impact on modern processors.