Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory

IEEE Trans. Parallel Distrib. Syst.

Acacio

et al. 2013

Self Cite

Hardware transactional memory (HTM) designs are very sensitive to the manner in which speculative updates from transactions are handled in the system. This study highlights how the lack of effective techniques for store management results in a quick degradation in the performance of eager HTM systems with increasing contention and, thus, lends credence to the belief that eager designs do not perform as well as their lazy counterparts when conflicts abound. In this work, we present two simple ways to improve handling of speculative stores-a way to effectively manage lines that exhibit migratory sharing and a way to hide store latency, particularly for those stores that target contended cache lines owned by other concurrent transactions. These two mechanisms yield substantial improvements in execution time when running applications with high contention, allowing eager designs to exceed the performance of lazy ones. Interestingly, the benefits that accrue from these enhancements can be at par with those achieved using more complex system-wide HTM techniques. Coupled with the fact that eager designs are easier to integrate into cache coherent architectures than lazy ones, we claim that with judicious management of stores they represent a more compelling design alternative.

“…In this paper, we extend the exploration of transactional store management presented in our previous work [16]. However, our primary focus now is on eager HTM designs.…”

Section: Introductionmentioning

confidence: 93%

“…As opposed to EE, lazy systems easily discard speculative state in a few cycles. However, the difference in execution time with LL_ideal_bufferL1 is less notable, as the number of contamination misses is large [16].…”

Section: Comparison Against Idealized Ll Systemsmentioning

confidence: 98%

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory

Titos-Gil

IEEE Trans. Parallel Distrib. Syst.

Acacio

et al. 2013

Self Cite

“…While store-buffers do provide this benefit to a certain extent, having the cache act as a precoherence buffer would potentially provide much larger performance benefits. Negi et al [2011] have studied the impact of such buffering on eager designs and found substantial performance gains could be achieved.…”

Section: Using the Cache Designs To Build An Htm Systemmentioning

confidence: 98%

SCIN-cache

ACM Trans. Archit. Code Optim.

Titos-Gil

2013

Self Cite

This article describes cache designs for efficiently supporting speculative techniques like transactional memory on chip multiprocessors with multithreaded cores. On-demand allocation and prompt freeing of speculative cache space in the design reduces the burden on nonspeculative execution. Quick access to both clean and speculative versions of data for multiple contexts provides flexibility and greater design freedom to HTM architects. Performance analysis shows the designs stand up well against other HTM design proposals, with potential performance gains in high contention applications with small transactions.

“…Prior work [17] has found that containing transactional stores in dedicated hardware buffers can mitigate overheads associated in reading back lines invalidated on an abort. However, our prefetching technique provides improvements in performance for fresh transaction invocations as well.…”

Section: Motivationmentioning

confidence: 99%

“…Yet others have attempted to incorporate the best of both eager and lazy policies in one design -at the granularity of application phases [19], at the granularity of transactions [15] , and at the granularity of cache lines [24]. There exist studies that have attempted to insulate the coherent cache hierarchy from adverse effects of repeated aborts [17]. These varied attempts at reducing overheads involved in shared data accesses by cooperating threads have motivated the design effort in this work.…”

Section: Related Workmentioning

confidence: 99%

Transactional prefetching

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

Armejach

Cristal

et al. 2012

Self Cite

Memory access latency is the primary performance bottleneck in modern computer systems. Prefetching data before it is needed by a processing core allows substantial performance gains by overlapping significant portions of memory latency with useful work. Prior work has investigated this technique and measured potential benefits in a variety of scenarios. However, its use in speeding up Hardware Transactional Memory (HTM) has remained hitherto unexplored. In several HTM designs transactions invalidate speculatively updated cache lines when they abort. Such cache lines tend to have high locality and are likely to be accessed again when the transaction re-executes. Coarse grained transactions that update several cache lines are particularly susceptible to performance degradation even under moderate contention. However, such transactions show strong locality of reference, especially when contention is high. Prefetching cache lines with high locality can, therefore, improve overall concurrency by speeding up transactions and, thereby, narrowing the window of time in which such transactions persist and can cause contention. Such transactions are important since they are likely to form a common TM use-case. We note that traditional prefetch techniques may not be able to track such lines adequately or issue prefetches quickly enough. This paper investigates the use of prefetching in HTMs, proposing a simple design to identify and request prefetch candidates, and measures performance gains to be had for several representative TM workloads.