Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Abstract

Abstract-Transactional Memory (TM) potentially simplifies parallel programming by providing atomicity and isolation for executed transactions. One of the key mechanisms to provide such properties is version management, which defines where and how transactional updates (new values) are stored. Version management can be implemented either eagerly or lazily. In Hardware Transactional Memory (HTM) implementations, eager version management puts new values in-place and old values are kept in a software log, while lazy version management stores new values in hardware buffers keeping old values in-place. Current HTM implementations, for both eager and lazy version management schemes, suffer from performance penalties due to the inability to handle two versions of the same logical data efficiently.In this paper, we introduce a reconfigurable L1 data cache architecture that has two execution modes: a 64KB general purpose mode and a 32KB TM mode which is able to manage two versions of the same logical data. The latter allows to handle old and new transactional values within the cache simultaneously when executing transactional workloads. We explain in detail the architectural design and internals of this Reconfigurable Data Cache (RDC), as well as the supported operations that allow to efficiently solve existing version management problems. We describe how the RDC can support both eager and lazy HTM systems, and we present two RDC-HTM designs. Our evaluation shows that the Eager-RDC-HTM and Lazy-RDC-HTM systems achieve 1.36× and 1.18× speedup, respectively, over state-of-theart proposals. We also evaluate the area and energy effects of our proposal, and we find that RDC designs are 1.92× and 1.38× more energy-delay efficient compared to baseline HTM systems, with less than 0.3% area impact on modern processors.

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications

“…This is because the N2 and N4 transistors that have been added to the feedback paths to enhance the robustness of the cell increase the driving loads in Q and QB, thus making the write operation slower. However, in typical applications, the number of read operations is considerably higher than the number of writes [29], [30], which alleviates the effect of slow writing and confirms the usefulness of the Nwise cell in cache circuits designs. There is also a much better balance between the read and write delays in Nwise compared to RHDB-10T.…”

An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory

“…There is a rich body of research on minimizing these overheads. For example, while TCC, UTM, VTM, LogTM, PTM, XTM, RTM, Scalable-TCC, ObjectTM, FasTM, Reconfigurable-TM, SEL-TM and SUV-TM [Hammond et al 2004]; [Ananian et al 2005]; [Rajwar et al 2005]; [Moore et al 2006]; [Chuang et al 2006]; [Chung et al 2006b]; [Shriraman et al 2007]; [Chafi et al 2007]; [Khan et al 2008]; [Lupon et al 2008] [Lupon et al 2009]; [Armejach et al 2011]; [Zhao et al 2012]; [Yan et al 2012] focus on reducing static overheads on version management, OneTM, DATM, SBCRHTM, ProactiveTM, EasyTM, DynTM, SON-TM, BFGTS-TM, 42:6 Z. Yan et al and ZEBRA [Blundell et al 2007]; [Ramadan et al 2008]; [Titos et al 2009]; [Blake et al 2009]; [Tomic et al 2009]; [Lupon et al 2010]; [Aydonat and Abdelrahman 2010]; [Blake et al 2011]; propose different TM architectures to alleviate the dynamic overheads incurred by transactional conflicts.…”

“…This basic function can sufficiently support flattened nested transactions, in which it only needs to hold the old value of the outermost transaction and the new value of the current transaction. This mode works like the reconfigurable cache [Armejach et al 2011] and SUV [Yan et al 2012] but without changing the existing hardware structure to reduce the data movements. In order to expose and exploit more thread-level parallelism, we extend the basic function of the pseudo-associative algorithm to invert the Nth most significant bit of the SET index to provide more slots than existing TCC with multi-tracking or associativity-based support [?…”

SCIN-cache

“…This can be noticed for certain benchmarks like intruder in numerous studies that use the STAMP benchmark suite [Cao Minh et al 2008] for evaluation. An attempt to tackle this problem has been made by Armejach et al [2011], proposing major changes to the highly optimized SRAM cell architectures in the cache. Each SRAM cell in the RDC is designed to store two bits of information with exchange circuits allowing the value of one bit to be copied to the other.…”