<title>Advanced silicon trench etching in MEMS applications</title>

Abstract

A high performance silicon dry etch process (STS Advanced Silicon Etch ASE) which in many cases is a beneficial replacement for the usual anisotropic wet etch methods like KOH etching is presented. During fabrication of Micro-Electro-Mechanical Systems (MEMS) the patterning ofsilicon is an essential step. Conventional wet or dry etching processes used up to now cannot meet the majority of future MEMS patterning needs. The process described in this paper allows a wide range of possible geometries and freedom of design and mask layout for novel MEMS applications. The installed etch system is working with an inductively coupled plasma source (ICP) which produces high plasma densities at low pressure to achieve deep silicon etching (> 200 vim) with high etch rates up to 5 jtm/min and a high passivation layer selectivity. The new ASE process uses only fluorine based chemistry and operates at room temperature. ASE uses photoresists and silicon oxid layers as an etch passivation and allows the manufacturing of silicon structures with nearly vertical side walls in bulk and surface micromachining illustrated by several MEMS applications carried out at the Fraunhofer Institute for Solid State Technology. With depths up to 100 jim realized at the institute now and an excellent anisotropic profile control ASE is obviously the tool, useful from device development to volume production of microsystems.

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

“…However, in terms of the practical fabrication, w 3 is retained to 3 μm and the trench depth (d 3 ) is set to 15 μm. Such a trench is able to be etched and filled with high quality [29]- [32]. When N dn-3 is set to be 2.2×10 16 cm −3 , BV can be larger than 500 V while the resistivity of RFP (ρ RFP ) is varying within a wide range.…”

Integrated fabrication of electrostatic microactuator for HDD R/W head positioning

“…For DRIE etching, the microloading effect (Kuehl et al 1988) must be considered in the process design and development. In order to minimize the microloading effect to get little variations on the highness of the comb drive structures, it is better to reduce the needed trench etching time besides optimizing layout pattern.…”

Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects

“…The Bosch process [46,47] enables etching of high aspect-ratio (AR) features in Si. This is a much desired characteristic as it helps overcome the density limitations of wet etching.…”

“…47 shows the form of a typical dynamic mode load-function that was used for characterizing the probe microsockets. The magnitude of the applied load was selected based on the quasi-static single indent measurements.…”