Low-pressure CMP for 300-mm ultra low-k (k=1.6-1.8)/Cu integration

Abstract

Toward the 45-nm technology node, multilevel C u dual-damascene interconnects with hybrid-structure low-k ILDs consisting of porous MSQ (k<1.6-1.8) and organic polymer films are successfully integrated on 300-mm wafers for the first time with a low-pressure CMP and dummy pattern technology, which supports the poor mechanical properties of ultra low-k films. IntroductionLow-k dielectrics have been extensively investigated as materials that can reduce the parasitic capacitance of ULSI interconnects. Porous low-k materials are thought to he the most promising for 45-65-nm technology nodes. Ultra low-k materials (k<Z.O), however, have a Young's modulus of less than 3 GPa (Fig. 1). This results in extreme difficulty in integrating ultra low-WCu interconnects due to CMP

Plasma-enhanced-chemical-vapor-deposited ultralow k for a postintegration porogen removal approach

“…[3][4][5] Moreover, the introduction of nanopores in a dielectric matrix drastically deteriorates the film mechanical properties which induces some limitations during the chemical mechanical polishing ͑CMP͒ and the packaging steps. 6 To overcome these issues, an integration scheme proposed by Calvert and Gallagher allows the solid phase processing of a spin-on porous low-k material. 7 As shown in Fig.…”

Process Technology for Copper Interconnects

“…There are a number of problems with Cu CMP in a porous low-k structure, including Cu dishing and insulator erosion, cracking and adhesion loss in the dielectric stack, and scratching or contamination of the low-k material by components or the slurry or reaction by-products [104][105][106][107][108]. The problems with dishing/erosion and cracking/adhesion loss can be minimized by reducing the downforce during CMP and improving the adhesion between layers in the stack [104].…”

“…The problems with dishing/erosion and cracking/adhesion loss can be minimized by reducing the downforce during CMP and improving the adhesion between layers in the stack [104]. There are two basic integration schemes for Cu CMP with porous low-k structures: the permanent polish stop method (Figure 8.16A-C) [104,105,109] and the direct CMP method ( Figure 8.16D-F) [109]. In the permanent polish stop approach, a relatively dense material, such as SiO 2 [104] or nonporous SiCOH [105,109], is used on top of the porous low-k material.…”

“…There are two basic integration schemes for Cu CMP with porous low-k structures: the permanent polish stop method (Figure 8.16A-C) [104,105,109] and the direct CMP method ( Figure 8.16D-F) [109]. In the permanent polish stop approach, a relatively dense material, such as SiO 2 [104] or nonporous SiCOH [105,109], is used on top of the porous low-k material. The advantage of this approach is that the porous low-k material is protected from CMP-related scratches and contamination.…”

Delamination analysis of Cu/low-k technology subjected to chemical-mechanical polishing process conditions

“…2 [7][8]. Accordingly, Kondo [9] have proposed the low-pressure CMP technique is proposed. However, as the size of the via of IC backend shrinks, the capability of the protecting the low-k material from delamination during CMP also decreases.…”