Low‐power CMOS variable gain amplifier based on a novel tunable transconductor

Sánchez-Rodríguez, T.; Gómez-Galán, Juan Antonio; Pedro, M.; López-Martín, Antonio J.; Carvajal, R.G.; Ramírez-Angulo, J.

doi:10.1049/iet-cds.2014.0130

Cited by 19 publications

(12 citation statements)

References 19 publications

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“…The input referred offsets are also very low, because of the large transistor sizes employed in this design. The simulated input offset is in a good agreement with theoretical predictions (see equation (20)). Table III illustrates the impact of temperature and V TH variations on PGA performance at minimum gain.…”

Section: Simulated Resultssupporting

confidence: 77%

“…CMRR≈A vo g mCMFB g mI 1 þ g m4;5 g ds4;5 þ g ds1À3 ! (21) where the indexes of g m and g ds refer to OTA I and g mCMFB = g mb19, 20 . The single-ended CMRR is relatively low (typically around 30 dB for A vo = 1 V/V), but increases with A vo .…”

Section: Cmrr and Psrr Performancementioning

confidence: 99%

“…This ensures equal voltage gains and equal GBW products for the common-mode and differential-mode loops in the system for N = 8. The channel area of M 19,20 required for the assumed value of σ(V OCM ) could be derived directly from (19) as:…”

Section: Pga Designmentioning

confidence: 99%

“…where δ is the assumed constant which defines the biasing currents and W/L parameters for all other transistors in CMFB/bias circuit (see section 3.3). The overall area of all transistors (M 15 -M 28 ) is given by (WL) Σ = (4 + 13δ)(WL) 19,20 and shows minimum for δ = 0.81. This value could be considered as optimum when the required area for the assumed value of σ(V OCM ) is considered.…”

Section: Pga Designmentioning

confidence: 99%

“…According to our survey, the VGA/PGA circuits presented so far in open literature were supplied with relatively large voltages, ranging from 1 V for ULP biomedical circuits [7], to several volts for high-frequency VGAs devoted to communication receivers [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Their architectures are rather not suitable for sub 0.5-V supply, because such a low supply voltage imposes specific design constraints and challenges.…”

Section: Introductionmentioning

confidence: 99%

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0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Circuit Theory & Apps

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A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18-μm complementary metal-oxide-semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6-dB steps. At minimum gain, the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 μV/Hz 1/2 , which results in a 63-dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5-pF load capacitance and the thirdorder input intercept point (IIP 3 ) is 1.62 V. The circuit performance was simulated with LTspice. Copyright

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Section: Simulated Resultssupporting

confidence: 77%

Section: Cmrr and Psrr Performancementioning

confidence: 99%

Section: Pga Designmentioning

confidence: 99%

Section: Pga Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Circuit Theory & Apps

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±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

Pourashraf

Ramírez-Angulo

López-Martín

et al. 2017

Circuit Theory & Apps

Self Cite

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A simple gate-driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op-amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18-V supply voltages in 0.18-μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4-bit digitally programmable gain and 0.7-Hz to 2-kHz true constant bandwidth that is independent on gain with a 25-pF load capacitor. In addition, simulations of the same circuit in 0.13-μm CMOS technology show that the proposed scheme allows operation with ±0.08-V supplies, 7.5-Hz to 8-kHz true constant bandwidth with a 25-pF load capacitor, and a total power dissipation of 0.07 μW. KEYWORDS floating battery, low voltage amplifier, nanowatt power consumption, programmable gain amplifier, true constant bandwidth | INTRODUCTIONA crucial aspect to reduce the power dissipation of analog and digital integrated systems is the reduction of their minimum supply requirements. For analog circuits based on op-amps, this can be achieved by keeping both amplifier input terminals close to a supply rail. Several papers have reported systems operating from supplies as low as 0.5 V (some without experimental verification). Most of them are bulk-driven (BD) circuits based on injecting input signals through the bulk terminal while connecting the gate to a supply rail 1-7 . The main disadvantage of the BD technique is that bulk transconductance is usually a factor 4-5 lower than the gate transconductance. This leads to essential gain bandwidth degradation, higher input noise, higher offset, etc. Also, input leakage currents (required to be supplied by the signal sources) can become comparable to the bias currents even for moderate input signal swings that weakly turn on the bulk PN junction. Additionally bulk driven circuits suffer from large bulk parasitic capacitances that results in large input capacitance. Other non-body driven (gate-driven (GD)) low voltage approaches use relatively large valued DC current sources to maintain both inputs of the op-amp close to a supply rail. The DC current sources are implemented with relatively low valued resistors. They increase essentially quiescent power dissipation and can also lead to a large output offset voltage and bandwidth degradation 7 . In this paper, we introduce a very simple technique to implement GD AC coupled amplifiers that can operate with ±0.18-V dual supply voltages V supply in 0.18-μm CMOS technology and ±0.08 V in 0.13-μm CMOS technology.

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