0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A simple gate-driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op-amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18-V supply voltages in 0.18-μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4-bit digitally programmable gain and 0.7-Hz to 2-kHz true constant bandwidth that is independent on gain with a 25-pF load capacitor. In addition, simulations of the same circuit in 0.13-μm CMOS technology show that the proposed scheme allows operation with ±0.08-V supplies, 7.5-Hz to 8-kHz true constant bandwidth with a 25-pF load capacitor, and a total power dissipation of 0.07 μW. KEYWORDS floating battery, low voltage amplifier, nanowatt power consumption, programmable gain amplifier, true constant bandwidth | INTRODUCTIONA crucial aspect to reduce the power dissipation of analog and digital integrated systems is the reduction of their minimum supply requirements. For analog circuits based on op-amps, this can be achieved by keeping both amplifier input terminals close to a supply rail. Several papers have reported systems operating from supplies as low as 0.5 V (some without experimental verification). Most of them are bulk-driven (BD) circuits based on injecting input signals through the bulk terminal while connecting the gate to a supply rail 1-7 . The main disadvantage of the BD technique is that bulk transconductance is usually a factor 4-5 lower than the gate transconductance. This leads to essential gain bandwidth degradation, higher input noise, higher offset, etc. Also, input leakage currents (required to be supplied by the signal sources) can become comparable to the bias currents even for moderate input signal swings that weakly turn on the bulk PN junction. Additionally bulk driven circuits suffer from large bulk parasitic capacitances that results in large input capacitance. Other non-body driven (gate-driven (GD)) low voltage approaches use relatively large valued DC current sources to maintain both inputs of the op-amp close to a supply rail. The DC current sources are implemented with relatively low valued resistors. They increase essentially quiescent power dissipation and can also lead to a large output offset voltage and bandwidth degradation 7 . In this paper, we introduce a very simple technique to implement GD AC coupled amplifiers that can operate with ±0.18-V dual supply voltages V supply in 0.18-μm CMOS technology and ±0.08 V in 0.13-μm CMOS technology.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

Pourashraf

Ramírez-Angulo

López-Martín

et al. 2017

A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

Shahpari

Habibi

2018

SummaryLow‐voltage high‐precision comparators are the main building blocks of many low‐power mixed‐mode electronic devices. In this paper, a rail‐to‐rail high‐precision comparator is introduced. The proposed comparator uses 2 parallel input P‐type metal‐oxide‐semiconductor pairs with a dynamic level shifter to ensure rail‐to‐rail operation. Moreover, the proposed circuit incorporates a rail‐to‐rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk‐tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail‐to‐rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180 nm complementary metal‐oxide‐semiconductor technology, and the results proved the rail‐to‐rail comparison ability in addition to the rail‐to‐rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non–rail‐to‐rail approach. The maximum clock frequency of the proposed circuit is 833 MHz, which is slightly more than its counterpart at similar operation conditions.

An ultra‐low‐power, low‐noise tunable electrocardiogram amplifier

Saeidian

Ashraf

2020

Summary The objective of this research work is to propose an innovative low‐power, low‐noise, tunable three‐stage capacitive instrumentation amplifier, capable of receiving and magnifying the electrocardiogram (ECG) signals. This is done by adding an extra stage to the second stage of the conventional capacitive instrumentation amplifier. The results show similar midband gain with lesser capacitor usage and smaller chip occupancy area with provision of concurrent tunable gain and bandwidth. The proposed amplifier is designed and implemented using TSMC 0.18‐μm CMOS technology scale under a 1‐V supply voltage with the simulation process carried out using Cadence Virtuoso tool. Post‐layout simulation results show that the amplifier has a tunable midband gain of 55 to 65.6 dB, low‐cutoff frequency tuned from 377 mHz to 4.5 Hz and high‐cutoff frequency tuned from 86.8 to 263.6 Hz. The simulated value of the input‐referred noise and noise efficiency factor (NEF) of the amplifier are 9.6 μVrms and 6.1, respectively, with the total power consumption of 71.2 nW.